"H. Peter Anvin" <hpa@xxxxxxxxx> writes: > Okay, I just had a scary and hopefully stupid thought. > > Especially Intel often has backchannels between the chipset and the > Ethernet controller for management functions -- anything from WoL to > IPMI -- generally over some kind of low-speed serial bus. > > We're not in a situation where the EEPROM can be touched from the > chipset via the SMBus or some other non-CPU channel? I know next to nothing about SMBus and especially those other backchannels, but the 82566 product brief :-) lists support for: - Intel Active Management Technology (AMT) with "System Defence" (whatever that means) - ASF 2.0 I think ASF (Alert Standard Format) is somehow related to IPMI and uses I^2C or something similar (SMBus). 8254x manual says that the EEPROM is divided into 4 parts: one for E1000 hw initialization, one for ASF (Ethernet in ASF mode?), one for external BMC (TCO) (loaded by external BMC from the SMBus) and one for software only (not used by hardware). Some chips only support #1 (and #4 of course). I understand the driver reads the EEPROM using EERD register (which, according to the manual, requires no additional locking) or drives the EEPROM directly, with a lock/unlock protocol (using EECD register). Now some devices lack the lock/unlock bits, but they lack ASF/BMC as well. I imagine chips other than 8254x may be different here. Do we have some "master" bugzilla entry or something like that for these problems? -- Krzysztof Halasa -- To unsubscribe from this list: send the line "unsubscribe kernel-testers" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
