On Wed, May 18, 2016 at 06:47:14PM +0200, Daniel Vetter wrote: > On bdw/hsw we have a separate psr dp aux registers to set up, but on > bdw it's shared with the main dp aux thing. Which means any subsequent > dp aux transaction will trample over it, and hence must be done > beforehand. > > Also this means we can't do any dp aux transactions while PSR is > active, or at least we must restore the old state. > > Probably need a psr disable/enable pair around dp aux transactions in > general. Yep. Looks like there's a note even in the HSW spec to forbid AUX while in PSR, even though it has the separate regs. "SRD AUX channel transactions must not be sent while DDI A AUX is being used. SRD must be completely disabled before a DDI A AUX channel transaction can be sent." > > Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> > Cc: Sonika Jindal <sonika.jindal@xxxxxxxxx> > Cc: Durgadoss R <durgadoss.r@xxxxxxxxx> > Cc: "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@xxxxxxxxx> > Signed-off-by: Daniel Vetter <daniel.vetter@xxxxxxxxx> Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_psr.c | 14 +++++++------- > 1 file changed, 7 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c > index a088be65a267..87805078c8a3 100644 > --- a/drivers/gpu/drm/i915/intel_psr.c > +++ b/drivers/gpu/drm/i915/intel_psr.c > @@ -197,6 +197,13 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp) > DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF, > DP_AUX_FRAME_SYNC_ENABLE); > > + if (dev_priv->psr.link_standby) > + drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, > + DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE); > + else > + drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, > + DP_PSR_ENABLE); > + > aux_ctl_reg = psr_aux_ctl_reg(dev_priv, port); > > /* Setup AUX registers */ > @@ -224,13 +231,6 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp) > (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | > (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT)); > } > - > - if (dev_priv->psr.link_standby) > - drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, > - DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE); > - else > - drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, > - DP_PSR_ENABLE); > } > > static void vlv_psr_enable_source(struct intel_dp *intel_dp) > -- > 2.8.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
