On ma, 2016-04-11 at 16:56 +0300, ville.syrjala@xxxxxxxxxxxxxxx wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> No clue what this is supposed to achieve. I think it's been there
> since
> the very beginning, so presumably some kind of kludge for very early
> silicon. Let's just throw it out.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 6 ------
> 1 file changed, 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c
> index 679f08c944ef..1d21ebfffd4d 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3319,12 +3319,6 @@ static void valleyview_irq_preinstall(struct
> drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> - /* VLV magic */
> - I915_WRITE(VLV_IMR, 0);
> - I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
> - I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
> - I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
> -
AFAICS this would also leave the ring interrupts unmasked before we
called ring->get_irq(), so at least the change is a fix for that. I
haven't found any explanation for the above either, so I guess the best
we can do at this point is to see if things continue to work without
it:
Reviewed-by: Imre Deak <imre.deak@xxxxxxxxx>
> gen5_gt_irq_reset(dev);
>
> I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
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