From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
There were two main causes for the VLV/CHV unclaimed register errors during
runtime PM transitons: dipslay irq setup and vlv_init_display_clock_gating().
This series reorganizes those things so that we only do them when the
disp2d power well is actually enabled.
Ville Syrjälä (10):
drm/i915: Remove "VLV magic" from irq setup
drm/i915: Fix up vlv/chv display irq setup
drm/i915: Skip display irq setup if display irqs aren't flagged as
enabled
drm/i915: Move vlv/chv display irq code to a more logical place
drm/i915: Clear display interrupt before enabling when turning on the
power well
drm/i915: Use GEN5_IRQ_INIT() in vlv_display_irq_postinstall()
drm/i915: Warn if irq_mask isn't ~0 during vlv/cvh display irq
postinstall
drm/i915: Move vlv_init_display_clock_gating() to the display power
well
drm/i915: Move DPINVGTT setup to vlv_display_irq_reset()
Revert "drm/i915: Limit the auto arming of mmio debugs on vlv/chv"
drivers/gpu/drm/i915/i915_irq.c | 217 +++++++++++---------------------
drivers/gpu/drm/i915/intel_pm.c | 15 ---
drivers/gpu/drm/i915/intel_runtime_pm.c | 13 ++
drivers/gpu/drm/i915/intel_uncore.c | 9 --
4 files changed, 89 insertions(+), 165 deletions(-)
--
2.7.4
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