On Fri, Jun 19, 2015 at 07:12:21PM +0100, Chris Wilson wrote: > On Fri, Jun 19, 2015 at 06:37:13PM +0100, Arun Siluvery wrote: > > In Indirect context w/a batch buffer, > > +WaFlushCoherentL3CacheLinesAtContextSwitch:bdw > > > > v2: Add LRI commands to set/reset bit that invalidates coherent lines, > > update WA to include programming restrictions and exclude CHV as > > it is not required (Ville) > > > > v3: Avoid unnecessary read when it can be done by reading register once (Chris). > > > > Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > > Cc: Dave Gordon <david.s.gordon@xxxxxxxxx> > > Signed-off-by: Rafael Barbalho <rafael.barbalho@xxxxxxxxx> > > Signed-off-by: Arun Siluvery <arun.siluvery@xxxxxxxxxxxxxxx> > > Acked-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> Merged up to this patch, thanks. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
