>From Gen8+ we have some workarounds that are applied Per context and they are applied using special batch buffers called as WA batch buffers. HW executes them at specific stages during context save/restore. The patches in this series adds this framework to i915. I did some basic testing on BDW by running glmark2 and didn't see any issues. These WA are mainly required when preemption is enabled. [v1] http://lists.freedesktop.org/archives/intel-gfx/2015-February/060707.html [v2] http://www.spinics.net/lists/intel-gfx/msg67804.html [v3] In v2, two separate ring_buffer objects were used to load WA instructions and they were part of every context which is not really required. Chris suggested a better approach of adding a page to context itself and using it for this purpose. Since GuC is also planning to do the same it can probably be shared with GuC. But after discussions it is agreed to use an independent page as GuC area might grow in future. Independent page also makes sense because these WA are only initialized once and not changed afterwards so we can share them across all contexts. [v4] Changes in this revision, In the previous version the size of batch buffers are fixed during initialization which is not a good idea. This is corrected by updating the functions that load WA to return the number of dwords written and caller updates the size once all WA are initialized. The functions now also accept offset field which allows us to have multiple batches so that required batch can be selected based on a criteria. This is not a requirement at this point but could be useful in future. WaFlushCoherentL3CacheLinesAtContextSwitch implementation was incomplete which is fixed and programming restrictions correctly applied. http://www.spinics.net/lists/intel-gfx/msg68947.html [v5] No major changes in this revision but switched to new revision as changes affected all patches. Introduced macro to add commands which also checks for page overflow. Moved code around to simplify, indentation fixes and other improvements suggested by Chris. Since we don't know the number of WA applied upfront, Chris suggested a two-pass approach but that brings additional complexity which is not necessary. Discussed with Chris and agreed upon on single page setup as simpler code wins and also single page is sufficient for our requirement. http://www.spinics.net/lists/intel-gfx/msg69176.html [v6] Changes made to make the code easy to modify for future Gen. It is much neater and contained now, big thanks to Chris Wilson for the review. Since these changes affect all patches I am sending as a separate revision. Please see the patches for more details. Arun Siluvery (6): drm/i915/gen8: Add infrastructure to initialize WA batch buffers drm/i915/gen8: Re-order init pipe_control in lrc mode drm/i915/gen8: Add WaDisableCtxRestoreArbitration workaround drm/i915/gen8: Add WaFlushCoherentL3CacheLinesAtContextSwitch workaround drm/i915/gen8: Add WaClearSlmSpaceAtContextSwitch workaround drm/i915/gen8: Add WaRsRestoreWithPerCtxtBb workaround drivers/gpu/drm/i915/i915_reg.h | 32 +++- drivers/gpu/drm/i915/intel_lrc.c | 328 +++++++++++++++++++++++++++++++- drivers/gpu/drm/i915/intel_ringbuffer.h | 21 ++ 3 files changed, 374 insertions(+), 7 deletions(-) -- 2.3.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
