On to, 2015-04-30 at 13:07 +0530, Vandana Kannan wrote:
> Second set of PPS registers have been defined but will be used when VBT
> provides a selection between the 2 sets of registers.
>
> Signed-off-by: Vandana Kannan <vandana.kannan@xxxxxxxxx>
> Signed-off-by: A.Sunil Kamath <sunil.kamath@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 580f5cb..199a1747 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6345,6 +6345,12 @@ enum skl_disp_power_wells {
> #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f)
> #define PANEL_POWER_CYCLE_DELAY_SHIFT 0
>
> +/* BXT PPS changes - 2nd set of PPS registers */
> +#define BXT_PP_STATUS2 0xc7300
> +#define BXT_PP_CONTROL2 0xc7304
> +#define BXT_PP_ON_DELAYS2 0xc7308
> +#define BXT_PP_OFF_DELAYS2 0xc730c
> +
Can we add these in the (future) patch which takes them into use?
> #define PCH_DP_B 0xe4100
> #define PCH_DPB_AUX_CH_CTL 0xe4110
> #define PCH_DPB_AUX_CH_DATA1 0xe4114
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