On Thu, 30 Apr 2015, Vandana Kannan <vandana.kannan@xxxxxxxxx> wrote: > Second set of PPS registers have been defined but will be used when VBT > provides a selection between the 2 sets of registers. > > Signed-off-by: Vandana Kannan <vandana.kannan@xxxxxxxxx> > Signed-off-by: A.Sunil Kamath <sunil.kamath@xxxxxxxxx> > --- > drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 580f5cb..199a1747 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -6345,6 +6345,12 @@ enum skl_disp_power_wells { > #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f) > #define PANEL_POWER_CYCLE_DELAY_SHIFT 0 > > +/* BXT PPS changes - 2nd set of PPS registers */ > +#define BXT_PP_STATUS2 0xc7300 > +#define BXT_PP_CONTROL2 0xc7304 > +#define BXT_PP_ON_DELAYS2 0xc7308 > +#define BXT_PP_OFF_DELAYS2 0xc730c > + > #define PCH_DP_B 0xe4100 > #define PCH_DPB_AUX_CH_CTL 0xe4110 > #define PCH_DPB_AUX_CH_DATA1 0xe4114 How about doing this patch first, with something like: diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 435c372d001e..a3af3526cb4f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6343,6 +6343,17 @@ enum skl_disp_power_wells { #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f) #define PANEL_POWER_CYCLE_DELAY_SHIFT 0 +/* BXT PPS changes - 2nd set of PPS registers */ +#define _BXT_PP_STATUS2 0xc7300 +#define _BXT_PP_CONTROL2 0xc7304 +#define _BXT_PP_ON_DELAYS2 0xc7308 +#define _BXT_PP_OFF_DELAYS2 0xc730c + +#define BXT_PP_STATUS(n) ((!n) ? PCH_PP_STATUS : _BXT_PP_STATUS2) +#define BXT_PP_CONTROL(n) ((!n) ? PCH_PP_CONTROL : _BXT_PP_CONTROL2) +#define BXT_PP_ON_DELAYS(n) ((!n) ? PCH_PP_ON_DELAYS : _BXT_PP_ON_DELAYS2) +#define BXT_PP_OFF_DELAYS(n) ((!n) ? PCH_PP_OFF_DELAYS : _BXT_PP_OFF_DELAYS2) + #define PCH_DP_B 0xe4100 #define PCH_DPB_AUX_CH_CTL 0xe4110 #define PCH_DPB_AUX_CH_DATA1 0xe4114 And you could use BXT_PP_* from the start. I believe this will add clarity to the usage and pinpoint where you'll need to touch the code to enable the 2nd power sequencer. BR, Jani. > -- > 2.0.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx