On Wed, 10 Sep 2014, Daniel Vetter <daniel@xxxxxxxx> wrote: > On Wed, Sep 10, 2014 at 01:01:58PM +0100, Chris Wilson wrote: >> After a GPU reset, we reinitialize RPS and RC6 state. (This may be >> unnecessary, they be preserved across the reset anyway...) Given that >> the GPU was active before the reset, it is likely that we do have a >> pending RPS work item and so we should simply disable it rather than >> emit a warn. >> >> Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > > This regression has been introduced in > > commit dd0a1aa19bd3d7203e58157b84cea78bbac605ac > Author: Jeff McGee <jeff.mcgee@xxxxxxxxx> > Date: Tue Feb 4 11:32:31 2014 -0600 > > drm/i915: Restore rps/rc6 on reset > > Cc: Jeff McGee <jeff.mcgee@xxxxxxxxx> > Cc: stable@xxxxxxxxxxxxxxx (under the assumption that it blew up in > reality and this isn't just a code audit exercise). I seem to have neglected this patch, and it no longer applies. Sorry. The warn seems to be still in place, please refresh the patch if the fix itself is still valid. Apologies and thanks, Jani. > > Adding Jeff. > -Daniel > >> --- >> drivers/gpu/drm/i915/intel_pm.c | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c >> index 9afdeed..3dea174 100644 >> --- a/drivers/gpu/drm/i915/intel_pm.c >> +++ b/drivers/gpu/drm/i915/intel_pm.c >> @@ -3694,7 +3694,7 @@ static void gen8_enable_rps_interrupts(struct drm_device *dev) >> struct drm_i915_private *dev_priv = dev->dev_private; >> >> spin_lock_irq(&dev_priv->irq_lock); >> - WARN_ON(dev_priv->rps.pm_iir); >> + dev_priv->rps.pm_iir = 0; >> gen8_enable_pm_irq(dev_priv, dev_priv->rps.pm_events); >> I915_WRITE(GEN8_GT_IIR(2), dev_priv->rps.pm_events); >> spin_unlock_irq(&dev_priv->irq_lock); >> @@ -3705,7 +3705,7 @@ static void gen6_enable_rps_interrupts(struct drm_device *dev) >> struct drm_i915_private *dev_priv = dev->dev_private; >> >> spin_lock_irq(&dev_priv->irq_lock); >> - WARN_ON(dev_priv->rps.pm_iir); >> + dev_priv->rps.pm_iir = 0; >> gen6_enable_pm_irq(dev_priv, dev_priv->rps.pm_events); >> I915_WRITE(GEN6_PMIIR, dev_priv->rps.pm_events); >> spin_unlock_irq(&dev_priv->irq_lock); >> -- >> 1.9.1 >> >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Daniel Vetter > Software Engineer, Intel Corporation > +41 (0) 79 365 57 48 - http://blog.ffwll.ch > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
