On 12/10/2014 2:50 PM, Daniel Vetter wrote:
On Tue, Dec 09, 2014 at 12:30:49PM +0200, Jani Nikula wrote:
On Tue, 09 Dec 2014, "Singh, Gaurav K" <gaurav.k.singh@xxxxxxxxx> wrote:
On 12/7/2014 4:13 PM, Gaurav K Singh wrote:
For DSI Port A & C, the seq_port value has been set to 0 now in VBT
Now the sequence of DSI single link on Port A and Port C will based
on the DVO port from VBT block 2.
Signed-off-by: Gaurav K Singh <gaurav.k.singh@xxxxxxxxx>
---
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index f8c2269..e7e2e52 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -110,7 +110,14 @@ static u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, u8 *data)
vc = (byte >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 0x3;
seq_port = (byte >> MIPI_PORT_SHIFT) & 0x3;
- port = intel_dsi_seq_port_to_port(seq_port);
+ /* For DSI Port A & C, the seq_port value has been set to 0 now in VBT
+ * Now the sequence of DSI single link on Port A and Port C will based
+ * on the DVO port from VBT block 2.
+ */
+ if (intel_dsi->ports == (1 << PORT_C))
+ port = PORT_C;
+ else
+ port = intel_dsi_seq_port_to_port(seq_port);
/* LP or HS mode */
intel_dsi->hs = mode;
Jani,
Need your reviewed-by on this patch too.
Okay, I was confused because there were actually five patches in this
four patch series! ;)
The *code* is
Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx>
because I understand it, but frankly both the commit message and the
comment confuse me more.
Hm, do you have suggestions for a better commit message? Should we just
drop the comment. I agree that the talk about VBT is really confusing and
smells like leftovers from other stuff.
I'll wait with this one until this is resolved. Accurate and clear commit
messages are important.
-Daniel
Jani,
How is the below commit message?
From now on for both DSI Ports A & C, the seq_port value has been set to 0.
seq_port value is parsed from Sequence block#53 of VBT.So, for packets that needs to be
read/write for DSI single link on Port A and Port C will based on the DVO port from VBT block 2.
With regards,
Gaurav
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