On 12/7/2014 4:13 PM, Gaurav K Singh wrote:
For DSI Port A & C, the seq_port value has been set to 0 now in VBT
Now the sequence of DSI single link on Port A and Port C will based
on the DVO port from VBT block 2.
Signed-off-by: Gaurav K Singh <gaurav.k.singh@xxxxxxxxx>
---
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index f8c2269..e7e2e52 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -110,7 +110,14 @@ static u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, u8 *data)
vc = (byte >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 0x3;
seq_port = (byte >> MIPI_PORT_SHIFT) & 0x3;
- port = intel_dsi_seq_port_to_port(seq_port);
+ /* For DSI Port A & C, the seq_port value has been set to 0 now in VBT
+ * Now the sequence of DSI single link on Port A and Port C will based
+ * on the DVO port from VBT block 2.
+ */
+ if (intel_dsi->ports == (1 << PORT_C))
+ port = PORT_C;
+ else
+ port = intel_dsi_seq_port_to_port(seq_port);
/* LP or HS mode */
intel_dsi->hs = mode;
Jani,
Need your reviewed-by on this patch too.
With regards,
Gaurav
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