2014-10-30 15:42 GMT-02:00 <ville.syrjala@xxxxxxxxxxxxxxx>:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> When disabling interrupts we do the writes in this order:
> IMR,IER,IIR,IIR. But when enabling interrupts we don't do use the
> mirrored order, and instead do IIR,IIR,IMR,IER.
>
> I like consistency unless there's a good reason against it, which I
> can't think of here, so change the enable order to IIR,IIR,IER,IMR.
I can't think of a reason either, so: Reviewed-by: Paulo Zanoni
<paulo.r.zanoni@xxxxxxxxx> .
Writing IMR after IER will also eliminate the super-tiny chance that
we'll get an interrupt after writing IMR but not IER, which means we
won't really get the interrupt itself, but still flip IIR :)
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index a2b013d..98a8d65 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -126,16 +126,16 @@ static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
>
> #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
> GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
> - I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
> I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
> - POSTING_READ(GEN8_##type##_IER(which)); \
> + I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
> + POSTING_READ(GEN8_##type##_IMR(which)); \
> } while (0)
>
> #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
> GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
> - I915_WRITE(type##IMR, (imr_val)); \
> I915_WRITE(type##IER, (ier_val)); \
> - POSTING_READ(type##IER); \
> + I915_WRITE(type##IMR, (imr_val)); \
> + POSTING_READ(type##IMR); \
> } while (0)
>
> /* For display hotplug interrupt */
> --
> 2.0.4
>
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--
Paulo Zanoni
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