From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
After enabling the pipe-a power well on CHV I noticed that hpd and interrupts
didn't work too well anymore. The reason is the same as on VLV; the power well
kills that stuff. So we need to get CHV to use the vlv display irq management
code. Thise series does that, and there's at least one patch just for VLV and
another one to apply a bit of ocd to the gen8 code.
After this series the CHV interupt code is starting to look somewhat decent,
mostly just calling a few VLV or gen8 helpers. And stuff actually works even
after the power well has gone off and back on. Obviously we have the same
limitation as VLV in that hpd and whatnot doesn't work while the power well
is off, but I think we've decided not to care about that for now.
Ville Syrjälä (14):
drm/i915: Apply some ocd for IMR vs. IER order during irq enable
drm/i915: Use DPINVGTT_STATUS_MASK
drm/i915: Use gen8_gt_irq_reset() in cherryview_irq_uninstall()
drm/i915: Drop the extra GEN8_PCU_IIR posting read from
cherryview_irq_preinstall()
drm/i915: Use a consistent order between IIR,IER,IMR writes on vlv/chv
drm/i915: Use GEN5_IRQ_RESET() on vlv/chv
drm/i915: Call gen5_gt_irq_reset() from valleyview_irq_uninstall()
drm/i915: Make valleyview_display_irqs_(un)install() work for chv
drm/i915: Refactor vlv_display_irq_reset()
drm/i915: Refactor vlv_display_irq_uninstall()
drm/i914: Refactor vlv_display_irq_postinstall()
drm/i915: Drop useless VLV_IIR writes from
vlv_display_irq_postinstall()
drm/i915: Use vlv display irq setup code for chv
drm/i915: Reinit display irqs and hpd from chv pipe-a power well
drivers/gpu/drm/i915/i915_irq.c | 199 ++++++++++++--------------------
drivers/gpu/drm/i915/intel_runtime_pm.c | 23 ++++
2 files changed, 94 insertions(+), 128 deletions(-)
--
2.0.4
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