BO allocations for pixmaps must be aligned to the tile height, but at some point the code was changed to align them to twice the tile height. This overallocates pixmaps, wasting memory, but more importantly, for buffers allocated by DRM and shared through DRI3, the stricter alignment check causes sharing to fail. >From reading through the history of the code and related bugs, it seems like this change was part of a set of changes trying to address what turned out to be a kernel regression. Reverting this change solves the DRI3 problem and saves a bit of memory for pixmap allocations. Signed-off-by: Keith Packard <keithp@xxxxxxxxxx> --- src/uxa/intel_uxa.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/uxa/intel_uxa.c b/src/uxa/intel_uxa.c index d33eca5..4ce6eae 100644 --- a/src/uxa/intel_uxa.c +++ b/src/uxa/intel_uxa.c @@ -206,7 +206,7 @@ intel_uxa_compute_size(struct intel_screen_private *intel, tile_height = 8; else tile_height = 32; - aligned_h = ALIGN(h, 2*tile_height); + aligned_h = ALIGN(h, tile_height); *stride = intel_get_fence_pitch(intel, ALIGN(pitch, 512), @@ -768,7 +768,7 @@ free_priv: else height = 32; - height = ALIGN(pixmap->drawable.height, 2*height); + height = ALIGN(pixmap->drawable.height, height); size = intel_get_fence_size(intel, priv->stride * height); } else size = priv->stride * pixmap->drawable.height; -- 2.0.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
