deepak.s@xxxxxxxxxxxxxxx writes:
> From: Deepak S <deepak.s@xxxxxxxxxxxxxxx>
>
> We need mem_freq or cz clock for freq/opcode conversion
>
> Signed-off-by: Deepak S <deepak.s@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
> drivers/gpu/drm/i915/intel_pm.c | 29 +++++++++++++++++++++++++++++
> 3 files changed, 36 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index bce4654..568b39c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -932,6 +932,7 @@ struct intel_gen6_power_mgmt {
> u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
> u8 rp1_freq; /* "less than" RP0 power/freqency */
> u8 rp0_freq; /* Non-overclocked max frequency. */
> + u32 cz_freq;
>
> u32 ei_interrupt_count;
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 490f031..e533efa 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5541,6 +5541,12 @@ enum punit_power_well {
> GEN6_PM_RP_DOWN_THRESHOLD | \
> GEN6_PM_RP_DOWN_TIMEOUT)
>
> +#define CHV_CZ_CLOCK_FREQ_MODE_200 200
> +#define CHV_CZ_CLOCK_FREQ_MODE_267 267
> +#define CHV_CZ_CLOCK_FREQ_MODE_320 320
> +#define CHV_CZ_CLOCK_FREQ_MODE_333 333
> +#define CHV_CZ_CLOCK_FREQ_MODE_400 400
> +
No need to define these in my opinion as it is 1:1. Just use
the numbers straight.
> #define GEN7_GT_SCRATCH_BASE 0x4F100
> #define GEN7_GT_SCRATCH_REG_NUM 8
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 9dfebab..6c19ce5 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5706,6 +5706,35 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
> static void cherryview_init_clock_gating(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> + u32 val;
> +
> + mutex_lock(&dev_priv->rps.hw_lock);
> + val = vlv_punit_read(dev_priv, CCK_FUSE_REG);
s/punit/cck (?)
With the changes mentioned above:
Reviewed-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxx>
> + mutex_unlock(&dev_priv->rps.hw_lock);
> + switch ((val >> 2) & 0x7) {
> + case 0:
> + case 1:
> + dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_200;
> + dev_priv->mem_freq = 1600;
> + break;
> + case 2:
> + dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_267;
> + dev_priv->mem_freq = 1600;
> + break;
> + case 3:
> + dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_333;
> + dev_priv->mem_freq = 2000;
> + break;
> + case 4:
> + dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_320;
> + dev_priv->mem_freq = 1600;
> + break;
> + case 5:
> + dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_400;
> + dev_priv->mem_freq = 1600;
> + break;
> + }
> + DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
>
> I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
>
> --
> 1.9.1
>
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