From: Deepak S <deepak.s@xxxxxxxxxxxxxxx> Enable RP1/RPn/RP0 sysfs and enable CHV PM interrupt for verifying the freq on VLV and CHV Deepak S (7): drm/i915: Read guaranteed freq for valleyview drm/i915: Add RP0/RP1/RPn render P state thresholds in VLV sysfs drm/i915: keep freq/opcode conversion function more generic drm/i915: populate mem_freq/cz_clock for chv drm/i915: CHV GPU frequency to opcode functions drm/i915/chv: Add basic PM interrupt support for CHV drm/i915: Add RP1 render P state thresholds in CHV drivers/gpu/drm/i915/i915_debugfs.c | 14 +-- drivers/gpu/drm/i915/i915_drv.h | 5 +- drivers/gpu/drm/i915/i915_irq.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 6 ++ drivers/gpu/drm/i915/i915_sysfs.c | 30 +++++-- drivers/gpu/drm/i915/intel_pm.c | 164 +++++++++++++++++++++++++++++++++--- 6 files changed, 189 insertions(+), 32 deletions(-) -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
