On Tue, Feb 11, 2014 at 08:19:13PM +0000, Chris Wilson wrote: > On Tue, Feb 11, 2014 at 07:52:06PM +0200, ville.syrjala@xxxxxxxxxxxxxxx wrote: > > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > > > According to BSpec the entire MI_DISPLAY_FLIP packet must be contained > > in a single cacheline. Make sure that happens. > > > > v2: Use intel_ring_begin_cacheline_safe() > > v3: Use intel_ring_cacheline_align() (Chris) > > > > Cc: Bjoern C <lkml@xxxxxxxxxxxx> > > Cc: Alexandru DAMIAN <alexandru.damian@xxxxxxxxx> > > Cc: Enrico Tagliavini <enrico.tagliavini@xxxxxxxxx> > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74053 > > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > I would have used intel_ring_align_cacheline() as it seems more natural > for me to say... > > Both, > Reviewed-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> Both merged to -fixes with cc: stable slapped on them. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
