On Tue, Feb 11, 2014 at 07:52:06PM +0200, ville.syrjala@xxxxxxxxxxxxxxx wrote: > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > According to BSpec the entire MI_DISPLAY_FLIP packet must be contained > in a single cacheline. Make sure that happens. > > v2: Use intel_ring_begin_cacheline_safe() > v3: Use intel_ring_cacheline_align() (Chris) > > Cc: Bjoern C <lkml@xxxxxxxxxxxx> > Cc: Alexandru DAMIAN <alexandru.damian@xxxxxxxxx> > Cc: Enrico Tagliavini <enrico.tagliavini@xxxxxxxxx> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74053 > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> I would have used intel_ring_align_cacheline() as it seems more natural for me to say... Both, Reviewed-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
