Re: [PATCH v5 7/7] drm/i915/dsc: Check if vblank is sufficient for dsc prefill

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On 1/15/2025 8:47 PM, Mitul Golani wrote:
High refresh rate panels which may have small line times
and vblank sizes, Check if vblank size is sufficient for
dsc prefill latency.

Bspec: 70151

Add Bspec as part of trailer.



--v2:
- Consider chroma downscaling factor in latency calculation. [Ankit]
- Replace with appropriate function name.

--v3:
- Remove FIXME tag.[Ankit]
- Replace Ycbcr444 to Ycbcr420.[Anit]
typo: Ankit
- Correct precision. [Ankit]
- Use some local valiables like linetime_factor and latency to
adjust precision.
- Declare latency to 0 initially to avoid returning any garbage values.
- Account for second scaler downscaling factor as well. [Ankit]

--v4:
- Improvise hscale and vscale calculation. [Ankit]
- Use appropriate name for number of scaler users. [Ankit]
- Update commit message and rebase.
- Add linetime and cdclk prefill adjustment calculation. [Ankit]

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@xxxxxxxxx>
---
  drivers/gpu/drm/i915/display/skl_watermark.c | 35 +++++++++++++++++++-
  1 file changed, 34 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index ca9d5677c356..13666adb8e36 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -2307,6 +2307,39 @@ cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state)
  				   2 * cdclk_state->logical.cdclk));
  }
+static int
+dsc_prefill_latency(const struct intel_crtc_state *crtc_state)
+{
+	const struct intel_crtc_scaler_state *scaler_state =
+						&crtc_state->scaler_state;
+	int latency = 0;
+	int num_scaler_users = hweight32(scaler_state->scaler_users);
+	int chroma_downscaling_factor =
+		crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;
+	long long hscale_k[2] = {0, 0};
+	long long vscale_k[2] = {0, 0};

Use u64 as mentioned in previous patch.

Regards,

Ankit

+
+	if (!crtc_state->dsc.compression_enable || !num_scaler_users)
+		return latency;
+
+	for (int i = 0; i < num_scaler_users; i++) {
+		hscale_k[i] =
+			max(1000, mul_u32_u32(scaler_state->scalers[i].hscale, 1000) >> 16);
+		vscale_k[i] =
+			max(1000, mul_u32_u32(scaler_state->scalers[i].vscale, 1000) >> 16);
+	}
+
+	latency  = DIV_ROUND_UP_ULL(hscale_k[0] * vscale_k[0], 1000000);
+
+	if (num_scaler_users > 1)
+		latency *= DIV_ROUND_UP_ULL(hscale_k[1] * vscale_k[1], 1000000);
+
+	latency *= DIV_ROUND_UP(15 * crtc_state->linetime, 10) * chroma_downscaling_factor *
+		   cdclk_prefill_adjustment(crtc_state);
+
+	return latency;
+}
+
  static int
  scaler_prefill_latency(const struct intel_crtc_state *crtc_state)
  {
@@ -2347,10 +2380,10 @@ skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state,
  	const struct drm_display_mode *adjusted_mode =
  		&crtc_state->hw.adjusted_mode;
- /* FIXME missing scaler and DSC pre-fill time */
  	return crtc_state->framestart_delay +
  		intel_usecs_to_scanlines(adjusted_mode, latency) +
  		scaler_prefill_latency(crtc_state) +
+		dsc_prefill_latency(crtc_state) +
  		wm0_lines >
  		adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start;
  }



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