> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Jouni
> Högander
> Sent: Thursday, 9 January 2025 12.35
> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx; intel-xe@xxxxxxxxxxxxxxxxxxxxx
> Cc: Hogander, Jouni <jouni.hogander@xxxxxxxxx>
> Subject: [PATCH 1/4] drm/i915/psr: Add new function for writing sink panel replay
> enable bit
>
> According to DP/eDP specification only DP_PANEL_REPLAY_ENABLE has to be set
> prior link training. For this purpose add a new function which sets this bit on sink
> side if Panel Replay is supported by the sink and the source.
>
Reviewed-by: Mika Kahola <mika.kahola@xxxxxxxxx>
> Signed-off-by: Jouni Högander <jouni.hogander@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 7 +++++++
> drivers/gpu/drm/i915/display/intel_psr.h | 1 +
> 2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 64c00a8a6850..e592bc01c7fb 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -827,6 +827,13 @@ void intel_psr_enable_sink(struct intel_dp *intel_dp,
> drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
> DP_SET_POWER_D0); }
>
> +void intel_psr_panel_replay_enable_sink(struct intel_dp *intel_dp) {
> + if (CAN_PANEL_REPLAY(intel_dp))
> + drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG,
> + DP_PANEL_REPLAY_ENABLE);
> +}
> +
> static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp) {
> struct intel_display *display = to_intel_display(intel_dp); diff --git
> a/drivers/gpu/drm/i915/display/intel_psr.h
> b/drivers/gpu/drm/i915/display/intel_psr.h
> index 956be263c09e..3b2643b83e06 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -30,6 +30,7 @@ bool intel_psr_needs_aux_io_power(struct intel_encoder
> *encoder, void intel_psr_init_dpcd(struct intel_dp *intel_dp); void
> intel_psr_enable_sink(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state);
> +void intel_psr_panel_replay_enable_sink(struct intel_dp *intel_dp);
> void intel_psr_pre_plane_update(struct intel_atomic_state *state,
> struct intel_crtc *crtc);
> void intel_psr_post_plane_update(struct intel_atomic_state *state,
> --
> 2.34.1
