== Series Details == Series: PSR DSB support URL : https://patchwork.freedesktop.org/series/142520/ State : warning == Summary == Error: dim checkpatch failed 934567a608a7 drm/i915/psr: Use PSR2_MAN_TRK_CTL CFF bit only to send full update 3ad4c4831274 drm/i915/psr: Rename psr_force_hw_tracking_exit as intel_psr_force_update acce01688b31 drm/i915/psr: Split setting sff and cff bits away from intel_psr_force_update 9834a8ae86e1 drm/i915/psr: Add register definitions for SFF_CTL and CFF_CTL registers -:24: WARNING:LONG_LINE: line length of 108 exceeds 100 columns #24: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:255: +#define LNL_SFF_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _LNL_SFF_CTL_A) -:28: WARNING:LONG_LINE: line length of 108 exceeds 100 columns #28: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:259: +#define LNL_CFF_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _LNL_CFF_CTL_A) total: 0 errors, 2 warnings, 0 checks, 14 lines checked 66b16e9ac4e6 drm/i915/psr: Ensure SFF/CFF bits are not written at their sample point 8d78f28353ca drm/i915/psr: Use SFF_CTL on invalidate/flush for LunarLake onwards ef0fb4a6ca27 drm/i915/psr: Allow writing PSR2_MAN_TRK_CTL using DSB b1e3b3f0e816 drm/i915/psr: Changes for PSR2_MAN_TRK_CTL handling when DSB is in use -:17: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?) #17: Taking PSR lock over DSB commit is not needed because PSR2_MAN_TRK_CTL is now total: 0 errors, 1 warnings, 0 checks, 17 lines checked 61449d56120e drm/i915/psr: Remove DSB_SKIP_WAITS_EN chicken bit 11408ce4840b drm/i915/psr: Allow DSB usage when PSR is enabled
