This patch set is doing necessary modifications to support PSR update
using DSB on LunarLake onwards
It is not necessary to wait for PSR1 to idle or PSR2 to exit DEEP
sleep at the begin of commit This is left out from DSB commit. There
might be room for optimization for non-DSB as well because such wait
is not supposed to be necessary at the begin of update.
PSR mutex is not locked when performing DSB commit. It is not
necessary as we are currently using DSB only when sending updates
towards panel. I.e. not using it when chaning PSR mode. Also necessary
changes are made to use PSR2_MAN_TRK_CTL only in DSB. Frontbuffer
updates and legacy cursor updates are using SFF_CTL register to
perform full frame updates.
Jouni Högander (10):
drm/i915/psr: Use PSR2_MAN_TRK_CTL CFF bit only to send full update
drm/i915/psr: Rename psr_force_hw_tracking_exit as
intel_psr_force_update
drm/i915/psr: Split setting sff and cff bits away from
intel_psr_force_update
drm/i915/psr: Add register definitions for SFF_CTL and CFF_CTL
registers
drm/i915/psr: Ensure SFF/CFF bits are not written at their sample
point
drm/i915/psr: Use SFF_CTL on invalidate/flush for LunarLake onwards
drm/i915/psr: Allow writing PSR2_MAN_TRK_CTL using DSB
drm/i915/psr: Changes for PSR2_MAN_TRK_CTL handling when DSB is in use
drm/i915/psr: Remove DSB_SKIP_WAITS_EN chicken bit
drm/i915/psr: Allow DSB usage when PSR is enabled
drivers/gpu/drm/i915/display/intel_display.c | 8 +-
drivers/gpu/drm/i915/display/intel_dsb.c | 5 +-
drivers/gpu/drm/i915/display/intel_psr.c | 134 +++++++++---------
drivers/gpu/drm/i915/display/intel_psr.h | 4 +-
drivers/gpu/drm/i915/display/intel_psr_regs.h | 8 ++
5 files changed, 87 insertions(+), 72 deletions(-)
--
2.34.1
