Re: [PATCH 13/13] drm/i915: do not save/restore backlight registers

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On Wed, 13 Nov 2013, Daniel Vetter <daniel@xxxxxxxx> wrote:
> On Fri, Nov 08, 2013 at 04:49:05PM +0200, Jani Nikula wrote:
>> The backlight enable code now has the smarts to do the right thing.
>> 
>> Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx>
>
> You can't just kill this due to ums code, instead it needs to be protected
> by if (!DRIVER_MODESET) checks.

/me cries a little.


> -Daniel
>
>> ---
>>  drivers/gpu/drm/i915/i915_drv.h     |    6 -----
>>  drivers/gpu/drm/i915/i915_suspend.c |   45 -----------------------------------
>>  2 files changed, 51 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 500bab3..6fec21e 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -766,13 +766,7 @@ struct i915_suspend_saved_registers {
>>  	u32 saveDSPATILEOFF;
>>  	u32 savePFIT_PGM_RATIOS;
>>  	u32 saveBLC_HIST_CTL;
>> -	u32 saveBLC_PWM_CTL;
>> -	u32 saveBLC_PWM_CTL2;
>>  	u32 saveBLC_HIST_CTL_B;
>> -	u32 saveBLC_PWM_CTL_B;
>> -	u32 saveBLC_PWM_CTL2_B;
>> -	u32 saveBLC_CPU_PWM_CTL;
>> -	u32 saveBLC_CPU_PWM_CTL2;
>>  	u32 saveFPB0;
>>  	u32 saveFPB1;
>>  	u32 saveDPLL_B;
>> diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
>> index eadf8e1..6b8fef7 100644
>> --- a/drivers/gpu/drm/i915/i915_suspend.c
>> +++ b/drivers/gpu/drm/i915/i915_suspend.c
>> @@ -192,7 +192,6 @@ static void i915_restore_vga(struct drm_device *dev)
>>  static void i915_save_display(struct drm_device *dev)
>>  {
>>  	struct drm_i915_private *dev_priv = dev->dev_private;
>> -	unsigned long flags;
>>  
>>  	/* Display arbitration control */
>>  	if (INTEL_INFO(dev)->gen <= 4)
>> @@ -203,46 +202,27 @@ static void i915_save_display(struct drm_device *dev)
>>  	if (!drm_core_check_feature(dev, DRIVER_MODESET))
>>  		i915_save_display_reg(dev);
>>  
>> -	spin_lock_irqsave(&dev_priv->backlight_lock, flags);
>> -
>>  	/* LVDS state */
>>  	if (HAS_PCH_SPLIT(dev)) {
>>  		dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
>> -		dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
>> -		dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
>> -		dev_priv->regfile.saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);
>> -		dev_priv->regfile.saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
>>  		if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
>>  			dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
>>  	} else if (IS_VALLEYVIEW(dev)) {
>>  		dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
>>  		dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
>>  
>> -		dev_priv->regfile.saveBLC_PWM_CTL =
>> -			I915_READ(VLV_BLC_PWM_CTL(PIPE_A));
>>  		dev_priv->regfile.saveBLC_HIST_CTL =
>>  			I915_READ(VLV_BLC_HIST_CTL(PIPE_A));
>> -		dev_priv->regfile.saveBLC_PWM_CTL2 =
>> -			I915_READ(VLV_BLC_PWM_CTL2(PIPE_A));
>> -		dev_priv->regfile.saveBLC_PWM_CTL_B =
>> -			I915_READ(VLV_BLC_PWM_CTL(PIPE_B));
>>  		dev_priv->regfile.saveBLC_HIST_CTL_B =
>>  			I915_READ(VLV_BLC_HIST_CTL(PIPE_B));
>> -		dev_priv->regfile.saveBLC_PWM_CTL2_B =
>> -			I915_READ(VLV_BLC_PWM_CTL2(PIPE_B));
>>  	} else {
>>  		dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
>>  		dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
>> -		dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
>>  		dev_priv->regfile.saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
>> -		if (INTEL_INFO(dev)->gen >= 4)
>> -			dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
>>  		if (IS_MOBILE(dev) && !IS_I830(dev))
>>  			dev_priv->regfile.saveLVDS = I915_READ(LVDS);
>>  	}
>>  
>> -	spin_unlock_irqrestore(&dev_priv->backlight_lock, flags);
>> -
>>  	if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
>>  		dev_priv->regfile.savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
>>  
>> @@ -278,7 +258,6 @@ static void i915_restore_display(struct drm_device *dev)
>>  {
>>  	struct drm_i915_private *dev_priv = dev->dev_private;
>>  	u32 mask = 0xffffffff;
>> -	unsigned long flags;
>>  
>>  	/* Display arbitration */
>>  	if (INTEL_INFO(dev)->gen <= 4)
>> @@ -287,12 +266,6 @@ static void i915_restore_display(struct drm_device *dev)
>>  	if (!drm_core_check_feature(dev, DRIVER_MODESET))
>>  		i915_restore_display_reg(dev);
>>  
>> -	spin_lock_irqsave(&dev_priv->backlight_lock, flags);
>> -
>> -	/* LVDS state */
>> -	if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
>> -		I915_WRITE(BLC_PWM_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
>> -
>>  	if (drm_core_check_feature(dev, DRIVER_MODESET))
>>  		mask = ~LVDS_PORT_EN;
>>  
>> @@ -305,13 +278,6 @@ static void i915_restore_display(struct drm_device *dev)
>>  		I915_WRITE(PFIT_CONTROL, dev_priv->regfile.savePFIT_CONTROL);
>>  
>>  	if (HAS_PCH_SPLIT(dev)) {
>> -		I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->regfile.saveBLC_PWM_CTL);
>> -		I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
>> -		/* NOTE: BLC_PWM_CPU_CTL must be written after BLC_PWM_CPU_CTL2;
>> -		 * otherwise we get blank eDP screen after S3 on some machines
>> -		 */
>> -		I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->regfile.saveBLC_CPU_PWM_CTL2);
>> -		I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->regfile.saveBLC_CPU_PWM_CTL);
>>  		I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
>>  		I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
>>  		I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
>> @@ -319,21 +285,12 @@ static void i915_restore_display(struct drm_device *dev)
>>  		I915_WRITE(RSTDBYCTL,
>>  			   dev_priv->regfile.saveMCHBAR_RENDER_STANDBY);
>>  	} else if (IS_VALLEYVIEW(dev)) {
>> -		I915_WRITE(VLV_BLC_PWM_CTL(PIPE_A),
>> -			   dev_priv->regfile.saveBLC_PWM_CTL);
>>  		I915_WRITE(VLV_BLC_HIST_CTL(PIPE_A),
>>  			   dev_priv->regfile.saveBLC_HIST_CTL);
>> -		I915_WRITE(VLV_BLC_PWM_CTL2(PIPE_A),
>> -			   dev_priv->regfile.saveBLC_PWM_CTL2);
>> -		I915_WRITE(VLV_BLC_PWM_CTL(PIPE_B),
>> -			   dev_priv->regfile.saveBLC_PWM_CTL);
>>  		I915_WRITE(VLV_BLC_HIST_CTL(PIPE_B),
>>  			   dev_priv->regfile.saveBLC_HIST_CTL);
>> -		I915_WRITE(VLV_BLC_PWM_CTL2(PIPE_B),
>> -			   dev_priv->regfile.saveBLC_PWM_CTL2);
>>  	} else {
>>  		I915_WRITE(PFIT_PGM_RATIOS, dev_priv->regfile.savePFIT_PGM_RATIOS);
>> -		I915_WRITE(BLC_PWM_CTL, dev_priv->regfile.saveBLC_PWM_CTL);
>>  		I915_WRITE(BLC_HIST_CTL, dev_priv->regfile.saveBLC_HIST_CTL);
>>  		I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
>>  		I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
>> @@ -341,8 +298,6 @@ static void i915_restore_display(struct drm_device *dev)
>>  		I915_WRITE(PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
>>  	}
>>  
>> -	spin_unlock_irqrestore(&dev_priv->backlight_lock, flags);
>> -
>>  	/* only restore FBC info on the platform that supports FBC*/
>>  	intel_disable_fbc(dev);
>>  	if (I915_HAS_FBC(dev)) {
>> -- 
>> 1.7.10.4
>> 
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch

-- 
Jani Nikula, Intel Open Source Technology Center
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