On Tue, 29 Oct 2024, Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx> wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Pull the audio min cdclk calculation into a helper and hide
> it inside intel_audio.c in order to keep most audio related
> details in one place.
>
> The one audio related thing that remains in intel_cdclk.c
> is commit 451eaa1a614c ("drm/i915: Bump GLK CDCLK frequency when
> driving multiple pipes") but given that's implemented in terms
> of the cdclk_state I think it should stay put.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_audio.c | 45 ++++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_audio.h | 1 +
> drivers/gpu/drm/i915/display/intel_cdclk.c | 37 +-----------------
> 3 files changed, 47 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
> index 32aa9ec1a204..82c45b24417a 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -978,6 +978,51 @@ static void glk_force_audio_cdclk(struct drm_i915_private *i915,
> drm_modeset_acquire_fini(&ctx);
> }
>
> +int intel_audio_min_cdclk(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_display *display = to_intel_display(crtc_state);
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> + int min_cdclk = 0;
> +
> + /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
> + * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
> + * there may be audio corruption or screen corruption." This cdclk
> + * restriction for GLK is 316.8 MHz.
> + */
> + if (intel_crtc_has_dp_encoder(crtc_state) &&
> + crtc_state->has_audio &&
> + crtc_state->port_clock >= 540000 &&
> + crtc_state->lane_count == 4) {
> + if (DISPLAY_VER(display) == 10) {
> + /* Display WA #1145: glk */
> + min_cdclk = max(316800, min_cdclk);
> + } else if (DISPLAY_VER(display) == 9 || IS_BROADWELL(dev_priv)) {
> + /* Display WA #1144: skl,bxt */
> + min_cdclk = max(432000, min_cdclk);
> + }
> + }
> +
> + /*
> + * According to BSpec, "The CD clock frequency must be at least twice
> + * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
> + */
> + if (crtc_state->has_audio && DISPLAY_VER(display) >= 9)
> + min_cdclk = max(2 * 96000, min_cdclk);
> +
> + /*
> + * "For DP audio configuration, cdclk frequency shall be set to
> + * meet the following requirements:
> + * DP Link Frequency(MHz) | Cdclk frequency(MHz)
> + * 270 | 320 or higher
> + * 162 | 200 or higher"
> + */
> + if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> + intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio)
> + min_cdclk = max(crtc_state->port_clock, min_cdclk);
> +
> + return min_cdclk;
> +}
> +
> static unsigned long i915_audio_component_get_power(struct device *kdev)
> {
> struct intel_display *display = to_intel_display(kdev);
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.h b/drivers/gpu/drm/i915/display/intel_audio.h
> index 576c061d72a4..1bafc155434a 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.h
> +++ b/drivers/gpu/drm/i915/display/intel_audio.h
> @@ -27,6 +27,7 @@ void intel_audio_codec_get_config(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state);
> void intel_audio_cdclk_change_pre(struct drm_i915_private *dev_priv);
> void intel_audio_cdclk_change_post(struct drm_i915_private *dev_priv);
> +int intel_audio_min_cdclk(const struct intel_crtc_state *crtc_state);
> void intel_audio_init(struct drm_i915_private *dev_priv);
> void intel_audio_register(struct drm_i915_private *i915);
> void intel_audio_deinit(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 3103ecab980c..89d12c521411 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2858,42 +2858,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
>
> min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);
> min_cdclk = max(hsw_ips_min_cdclk(crtc_state), min_cdclk);
> -
> - /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
> - * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
> - * there may be audio corruption or screen corruption." This cdclk
> - * restriction for GLK is 316.8 MHz.
> - */
> - if (intel_crtc_has_dp_encoder(crtc_state) &&
> - crtc_state->has_audio &&
> - crtc_state->port_clock >= 540000 &&
> - crtc_state->lane_count == 4) {
> - if (DISPLAY_VER(display) == 10) {
> - /* Display WA #1145: glk */
> - min_cdclk = max(316800, min_cdclk);
> - } else if (DISPLAY_VER(display) == 9 || IS_BROADWELL(dev_priv)) {
> - /* Display WA #1144: skl,bxt */
> - min_cdclk = max(432000, min_cdclk);
> - }
> - }
> -
> - /*
> - * According to BSpec, "The CD clock frequency must be at least twice
> - * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
> - */
> - if (crtc_state->has_audio && DISPLAY_VER(display) >= 9)
> - min_cdclk = max(2 * 96000, min_cdclk);
> -
> - /*
> - * "For DP audio configuration, cdclk frequency shall be set to
> - * meet the following requirements:
> - * DP Link Frequency(MHz) | Cdclk frequency(MHz)
> - * 270 | 320 or higher
> - * 162 | 200 or higher"
> - */
> - if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> - intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio)
> - min_cdclk = max(crtc_state->port_clock, min_cdclk);
> + min_cdclk = max(intel_audio_min_cdclk(crtc_state), min_cdclk);
>
> /*
> * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
--
Jani Nikula, Intel
