On Tue, 29 Oct 2024, Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx> wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Pull the whole BDW IPS min CDCLK stuff into the IPS code
> so that all the details around IPS are contained in once
> place.
>
> Note that while
> - min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95);
> vs.
> + min_cdclk = max(DIV_ROUND_UP(crtc_state->pixel_rate * 100, 95), min_cdclk)
> may look different, they are in fact the same because
> min_cdclk==crtc_state->pixel_rate at this point in
> intel_crtc_compute_min_cdclk() on BDW.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/hsw_ips.c | 16 +++++++++++++++-
> drivers/gpu/drm/i915/display/hsw_ips.h | 6 +++---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 5 +----
> 3 files changed, 19 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i915/display/hsw_ips.c
> index c571c6e76d4a..5a0fc9f2bd6f 100644
> --- a/drivers/gpu/drm/i915/display/hsw_ips.c
> +++ b/drivers/gpu/drm/i915/display/hsw_ips.c
> @@ -186,7 +186,7 @@ bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
> return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
> }
>
> -bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
> +static bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> @@ -215,6 +215,20 @@ bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
> return true;
> }
>
> +int hsw_ips_min_cdclk(const struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> +
> + if (!IS_BROADWELL(i915))
> + return 0;
> +
> + if (!hsw_crtc_state_ips_capable(crtc_state))
> + return 0;
> +
> + /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
> + return DIV_ROUND_UP(crtc_state->pixel_rate * 100, 95);
> +}
> +
> int hsw_ips_compute_config(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> diff --git a/drivers/gpu/drm/i915/display/hsw_ips.h b/drivers/gpu/drm/i915/display/hsw_ips.h
> index 35364228e1c1..7af12f88a8ce 100644
> --- a/drivers/gpu/drm/i915/display/hsw_ips.h
> +++ b/drivers/gpu/drm/i915/display/hsw_ips.h
> @@ -19,7 +19,7 @@ bool hsw_ips_pre_update(struct intel_atomic_state *state,
> void hsw_ips_post_update(struct intel_atomic_state *state,
> struct intel_crtc *crtc);
> bool hsw_crtc_supports_ips(struct intel_crtc *crtc);
> -bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
> +int hsw_ips_min_cdclk(const struct intel_crtc_state *crtc_state);
> int hsw_ips_compute_config(struct intel_atomic_state *state,
> struct intel_crtc *crtc);
> void hsw_ips_get_config(struct intel_crtc_state *crtc_state);
> @@ -42,9 +42,9 @@ static inline bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
> {
> return false;
> }
> -static inline bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
> +static inline int hsw_ips_min_cdclk(const struct intel_crtc_state *crtc_state)
> {
> - return false;
> + return 0;
> }
> static inline int hsw_ips_compute_config(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 977fcdaa7372..3103ecab980c 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2857,10 +2857,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
> return 0;
>
> min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);
> -
> - /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
> - if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state))
> - min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95);
> + min_cdclk = max(hsw_ips_min_cdclk(crtc_state), min_cdclk);
>
> /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
> * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
--
Jani Nikula, Intel
