On Thu, Nov 7, 2013 at 7:46 PM, Ben Widawsky <ben@xxxxxxxxxxxx> wrote: > On Thu, Nov 07, 2013 at 07:36:50PM +0100, Daniel Vetter wrote: >> On Thu, Nov 7, 2013 at 7:11 PM, Ben Widawsky <ben@xxxxxxxxxxxx> wrote: >> >> > @@ -63,7 +65,7 @@ static void exec(int fd, uint32_t handle, uint32_t offset) >> >> > gem_exec[0].relocs_ptr = (uintptr_t) gem_reloc; >> >> > gem_exec[0].alignment = 0; >> >> > gem_exec[0].offset = 0; >> >> > - gem_exec[0].flags = 0; >> >> > + gem_exec[0].flags = LOCAL__EXEC_OBJ_NEEDS_GTT; >> >> >> >> This only really works with the aliasing ppgtt stuff on gen6, I'd just >> >> skip the test -it's not really useful with real ppgtt. >> >> -Daniel >> > >> > It is really useful with real ppgtt. Please rethink your assertion. >> >> The test links up the global gtt used by the current pin ioctl with >> the ppgtt. That's not useful, except when they alias. If we want >> soft-pinning, then we need a new ioctl mode to return the right >> address from the right address space. Which means a new (sub)test. >> -Daniel > > This is only indirectly related to soft pinning. No context will ever have the > global GTT address space. If you want to support the pin IOCTL, (which > Chris has before said he requires - the original patch series disabled > it) you must do this. We already have a flag that does what we want, > and, demonstrably, a test which exercises it. > > I do not think a new ioctl, nor a new subtest is the solution for this. Ok, I'll wait until I see the code that implements this on top of ppgtt. But until we have that I don't think we need to change the test at all. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
