To support Link M/N ratio between 10.0 and 15.0, for some BMG ultrajoiner
cases we need Wa_14021768792.
To bypass the hardware limitation within the Timing Generator DDA (TGDDA),
we need to program the LINKM and LINKN registers as defined in
the WA. Along with this we also need relvant bits in HDMI_EMP_DATA and
CHICKEN_TRANS regs.
Add the bits for the WA and a new member 'bmg_bypass_m_n_ratio_limit' to
track if we need to bypass the Link M/N ratio limit in intel_link_m_n
structure.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@xxxxxxxxx>
---
drivers/gpu/drm/i915/display/intel_display.c | 79 ++++++++++++++++++-
.../drm/i915/display/intel_display_types.h | 2 +
drivers/gpu/drm/i915/i915_reg.h | 5 ++
3 files changed, 83 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a28500d5f969..d23f90096b0e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2683,6 +2683,19 @@ bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv);
}
+static
+void bmg_bypass_m_n_limit_write(struct intel_crtc *crtc,
+ enum transcoder transcoder,
+ const struct intel_link_m_n *m_n)
+{
+ struct intel_display *display = to_intel_display(crtc);
+ int m_n_frac = m_n->link_m % m_n->link_n;
+ enum pipe pipe = crtc->pipe;
+
+ intel_de_rmw(display, MTL_CHICKEN_TRANS(transcoder), 0, BMG_DP_BYPASS_M_N_LIMIT);
+ intel_de_write(display, HDMI_EMP_DATA(pipe), m_n_frac);
+}
+
void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
enum transcoder transcoder,
const struct intel_link_m_n *m_n)
@@ -2700,6 +2713,9 @@ void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
intel_set_m_n(dev_priv, m_n,
PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
+
+ if (m_n->bypass_m_n_ratio_limit)
+ bmg_bypass_m_n_limit_write(crtc, transcoder, m_n);
}
void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
@@ -2716,6 +2732,9 @@ void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
PIPE_DATA_N2(dev_priv, transcoder),
PIPE_LINK_M2(dev_priv, transcoder),
PIPE_LINK_N2(dev_priv, transcoder));
+
+ if (m_n->bypass_m_n_ratio_limit)
+ bmg_bypass_m_n_limit_write(crtc, transcoder, m_n);
}
static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
@@ -3394,12 +3413,51 @@ void intel_get_m_n(struct drm_i915_private *i915,
m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1;
}
+static
+void bmg_bypass_m_n_limit_read(struct intel_crtc *crtc,
+ enum transcoder transcoder,
+ struct intel_link_m_n *m_n)
+{
+ struct intel_display *display = to_intel_display(crtc);
+ enum pipe pipe = crtc->pipe;
+ u32 chicken_trans, m_n_frac;
+
+ chicken_trans = intel_de_read(display, MTL_CHICKEN_TRANS(transcoder));
+ m_n_frac = intel_de_read(display, HDMI_EMP_DATA(pipe));
+
+ if ((chicken_trans & BMG_DP_BYPASS_M_N_LIMIT) &&
+ m_n_frac == (m_n->link_m % m_n->link_n))
+ m_n->bypass_m_n_ratio_limit = true;
+}
+
+static
+int bmg_can_bypass_m_n_limit(struct intel_display *display,
+ int m_n_ratio,
+ enum pipe pipe)
+{
+ struct drm_i915_private *i915 = to_i915(display->drm);
+
+ if (DISPLAY_VER(display) != 14 || !IS_DGFX(i915) ||
+ !IS_DISPLAY_STEP(display, STEP_C0, STEP_FOREVER))
+ return false;
+
+ if (pipe != PIPE_A)
+ return false;
+
+ if (m_n_ratio > 15)
+ return false;
+
+ return true;
+}
+
void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
enum transcoder transcoder,
struct intel_link_m_n *m_n)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc);
enum pipe pipe = crtc->pipe;
+ int m_n_ratio;
if (DISPLAY_VER(dev_priv) >= 5)
intel_get_m_n(dev_priv, m_n,
@@ -3411,6 +3469,11 @@ void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
intel_get_m_n(dev_priv, m_n,
PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
+
+ m_n_ratio = DIV_ROUND_UP(m_n->link_m, m_n->link_n);
+
+ if (bmg_can_bypass_m_n_limit(display, m_n_ratio, pipe))
+ bmg_bypass_m_n_limit_read(crtc, transcoder, m_n);
}
void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
@@ -3418,6 +3481,9 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
struct intel_link_m_n *m_n)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc);
+ enum pipe pipe = crtc->pipe;
+ int m_n_ratio;
if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder))
return;
@@ -3427,6 +3493,11 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
PIPE_DATA_N2(dev_priv, transcoder),
PIPE_LINK_M2(dev_priv, transcoder),
PIPE_LINK_N2(dev_priv, transcoder));
+
+ m_n_ratio = DIV_ROUND_UP(m_n->link_m, m_n->link_n);
+
+ if (bmg_can_bypass_m_n_limit(display, m_n_ratio, pipe))
+ bmg_bypass_m_n_limit_read(crtc, transcoder, m_n);
}
static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
@@ -5175,20 +5246,22 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
if (!intel_compare_link_m_n(¤t_config->name, \
&pipe_config->name)) { \
pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
- "(expected tu %i data %i/%i link %i/%i link_n_ext %i, " \
- "found tu %i, data %i/%i link %i/%i link_n_ext %i)", \
+ "(expected tu %i data %i/%i link %i/%i link_n_ext %i bypass_m_n_ratio_limit %s, " \
+ "found tu %i, data %i/%i link %i/%i link_n_ext %i bypass_m_n_ratio_limit %s)", \
current_config->name.tu, \
current_config->name.data_m, \
current_config->name.data_n, \
current_config->name.link_m, \
current_config->name.link_n, \
current_config->name.link_n_ext, \
+ str_yes_no(current_config->name.bypass_m_n_ratio_limit), \
pipe_config->name.tu, \
pipe_config->name.data_m, \
pipe_config->name.data_n, \
pipe_config->name.link_m, \
pipe_config->name.link_n, \
- pipe_config->name.link_n_ext); \
+ pipe_config->name.link_n_ext, \
+ str_yes_no(pipe_config->name.bypass_m_n_ratio_limit)); \
ret = false; \
} \
} while (0)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 1328e2e89786..d7ea7d437a6d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1029,6 +1029,8 @@ struct intel_link_m_n {
u32 link_m;
u32 link_n;
u8 link_n_ext;
+ /* Wa_14021768792 for linkm/n ratio > 10 */
+ bool bypass_m_n_ratio_limit;
};
struct intel_csc_matrix {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 941d273dbf8c..4e16a129d891 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1110,6 +1110,10 @@
#define _TRANS_VSYNCSHIFT_A 0x60028
#define _TRANS_MULT_A 0x6002c
+#define _HDMI_EMP_DATA_A 0x600d8
+#define _HDMI_EMP_DATA_B 0x610d8
+#define HDMI_EMP_DATA(pipe) _MMIO_PIPE(pipe, _HDMI_EMP_DATA_A, _HDMI_EMP_DATA_B)
+
/* Pipe/transcoder B timing regs */
#define _TRANS_HTOTAL_B 0x61000
#define _TRANS_HBLANK_B 0x61004
@@ -2802,6 +2806,7 @@
#define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15)
#define DP_FEC_BS_JITTER_WA REG_BIT(15)
#define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12)
+#define BMG_DP_BYPASS_M_N_LIMIT REG_BIT(11)
#define DP_DSC_INSERT_SF_AT_EOL_WA REG_BIT(4)
#define HDCP_LINE_REKEY_DISABLE REG_BIT(0)
--
2.45.2
