For Platforms that support higher link rates, there is a limitation on
Link M /Link N ratio.
If the CEILING( Link M / Link N ) ratio is greater than 10.0, then
hardware cannot support the given resolution / refresh rate at the given
configuration.
For BMG Wa_14021768792 helps to bypass this limitation and allows it to
support the ratio till 15.0.
This series adds the missing restrictions for earlier platforms and adds
the Wa_14021768792 for BMG as per Bspec:49266
Ankit Nautiyal (5):
drm/i915/display: Add bits for link_n_exended for DISPLAY >= 14
drm/i915/display: Limit m/n ratio to 10 for display > 12
drm/i915/display: Add bits for Wa_14021768792 for linkm/n ratio > 10
drm/i915/display: Implement Wa_14021768792 for BMG DP for link_m/n
ratio > 10
drm/i915: Add Wa_14021768792 as per WA framework
drivers/gpu/drm/i915/display/intel_display.c | 132 ++++++++++++++++--
drivers/gpu/drm/i915/display/intel_display.h | 14 +-
.../drm/i915/display/intel_display_types.h | 3 +
.../gpu/drm/i915/display/intel_display_wa.h | 2 +
drivers/gpu/drm/i915/display/intel_dp.c | 66 +++++++--
drivers/gpu/drm/i915/display/intel_dp.h | 5 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 37 +++--
drivers/gpu/drm/i915/display/intel_fdi.c | 15 +-
drivers/gpu/drm/i915/i915_reg.h | 7 +
drivers/gpu/drm/xe/display/xe_display_wa.c | 5 +
drivers/gpu/drm/xe/xe_wa_oob.rules | 1 +
11 files changed, 241 insertions(+), 46 deletions(-)
--
2.45.2
