> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@xxxxxxxxx>
> Sent: Friday, August 23, 2024 3:26 PM
> To: Bhadane, Dnyaneshwar <dnyaneshwar.bhadane@xxxxxxxxx>
> Cc: intel-gfx@xxxxxxxxxxxxxxxxxxxxx; Chery, Nanley G <nanley.g.chery@xxxxxxxxx>
> Subject: Re: [PATCH] drm/i915/gt: Disable Redundant HZ Plane expansions for MTL/ARL and DG2
>
> On Fri, Aug 23, 2024 at 03:40:09PM +0530, Dnyaneshwar Bhadane wrote:
> > Program HZ Plane disable bit to 1 to stop sending the redundant
> > plane expansions.
> >
> > Bspec: 68331
> >
> > Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@xxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 +++--
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 17 +++++++++++++++--
> > 2 files changed, 18 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > index e42b3a5d4e63..74b633a78eda 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > @@ -446,8 +446,9 @@
> >
> > /* GEN7 chicken */
> > #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
> > -#define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC (1 << 10)
> > -#define GEN9_RHWO_OPTIMIZATION_DISABLE (1 << 14)
> > +#define GEN9_RHWO_OPTIMIZATION_DISABLE REG_BIT(14)
> > +#define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC REG_BIT(10)
> > +#define HIZ_PLANE_OPTIMIZATION_DISABLE REG_BIT(9)
> >
> > #define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
> > #define GEN9_PBE_COMPRESSED_HASH_SELECTION (1 << 13)
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index bfe6d8fc820f..ff257bb2d15a 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -1550,6 +1550,13 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> >
> > /* Wa_14010648519:dg2 */
> > wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE);
> > +
> > + /*
> > + * DisableHIZPlaneOptimizationForRedundantZPlaneUnit
> > + * This is not WA,THis is required by recommended tuning setting.
> > + */
> > + wa_masked_dis(wal,
> > + GEN7_COMMON_SLICE_CHICKEN1, HIZ_PLANE_OPTIMIZATION_DISABLE);
>
> The bspec's performance guide page says that this should be done
> selectively, on a workload-specific basis when certain conditions are
> met. So we don't want to set the value of this bit directly in the KMD
> because we don't know anything about the workloads being executed. We
> just want to make the register writable from userspace so that they can
> flip this bit themselves when it's appropriate. The
> {dg2,xelp}_whitelist_build changes you have farther down take care of
> granting userspace access to do this; we can drop the changes here to
> the {dg2,xelpg}_gt_workarounds_init functions.
>
> From a quick skim of the Mesa source code, it looks like Mesa is only
> setting this register bit right now on the older gen12 platforms to
> address Wa_1808121037 (in src/intel/vulkan/genX_cmd_buffer.c and
> src/gallium/drivers/iris/iris_state.c), but I don't see them setting
> this anywhere that isn't guarded by "#if INTEL_NEEDS_WA_1808121037" yet.
> They might not have seen the update in the performance guide, or they
> might have been waiting for us to whitelist the register on these
> platforms before adding their implementation.
>
> +Cc Nanley from the Mesa team since he implemented the Wa_1808121037
> code and will probably know best if/how the Mesa code should be updated
> to also address the DG2 + MTL performance tuning setting recommended on
> bspec 68331.
>
Thanks for the heads up! I'll file an mesa issue about this.
-Nanley
>
> Matt
>
> > }
> >
> > static void
> > @@ -1570,6 +1577,12 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> > /* Wa_14015795083 */
> > wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
> > }
> > + /*
> > + * DisableHIZPlaneOptimizationForRedundantZPlaneUnit
> > + * This is not WA, This is required by recommended tuning setting.
> > + */
> > + wa_masked_dis(wal,
> > + GEN7_COMMON_SLICE_CHICKEN1, HIZ_PLANE_OPTIMIZATION_DISABLE);
> >
> > /*
> > * Unlike older platforms, we no longer setup implicit steering here;
> > @@ -2072,7 +2085,7 @@ static void dg2_whitelist_build(struct intel_engine_cs *engine)
> > case RENDER_CLASS:
> > /* Required by recommended tuning setting (not a workaround) */
> > whitelist_mcr_reg(w, XEHP_COMMON_SLICE_CHICKEN3);
> > -
> > + whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1);
> > break;
> > default:
> > break;
> > @@ -2087,7 +2100,7 @@ static void xelpg_whitelist_build(struct intel_engine_cs *engine)
> > case RENDER_CLASS:
> > /* Required by recommended tuning setting (not a workaround) */
> > whitelist_mcr_reg(w, XEHP_COMMON_SLICE_CHICKEN3);
> > -
> > + whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1);
> > break;
> > default:
> > break;
> > --
> > 2.34.1
> >
>
> --
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation
