Program HZ Plane disable bit to 1 to stop sending the redundant plane expansions. Bspec: 68331 Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@xxxxxxxxx> --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 +++-- drivers/gpu/drm/i915/gt/intel_workarounds.c | 17 +++++++++++++++-- 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index e42b3a5d4e63..74b633a78eda 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -446,8 +446,9 @@ /* GEN7 chicken */ #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010) -#define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC (1 << 10) -#define GEN9_RHWO_OPTIMIZATION_DISABLE (1 << 14) +#define GEN9_RHWO_OPTIMIZATION_DISABLE REG_BIT(14) +#define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC REG_BIT(10) +#define HIZ_PLANE_OPTIMIZATION_DISABLE REG_BIT(9) #define COMMON_SLICE_CHICKEN2 _MMIO(0x7014) #define GEN9_PBE_COMPRESSED_HASH_SELECTION (1 << 13) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index bfe6d8fc820f..ff257bb2d15a 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1550,6 +1550,13 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) /* Wa_14010648519:dg2 */ wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE); + + /* + * DisableHIZPlaneOptimizationForRedundantZPlaneUnit + * This is not WA,THis is required by recommended tuning setting. + */ + wa_masked_dis(wal, + GEN7_COMMON_SLICE_CHICKEN1, HIZ_PLANE_OPTIMIZATION_DISABLE); } static void @@ -1570,6 +1577,12 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) /* Wa_14015795083 */ wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); } + /* + * DisableHIZPlaneOptimizationForRedundantZPlaneUnit + * This is not WA, This is required by recommended tuning setting. + */ + wa_masked_dis(wal, + GEN7_COMMON_SLICE_CHICKEN1, HIZ_PLANE_OPTIMIZATION_DISABLE); /* * Unlike older platforms, we no longer setup implicit steering here; @@ -2072,7 +2085,7 @@ static void dg2_whitelist_build(struct intel_engine_cs *engine) case RENDER_CLASS: /* Required by recommended tuning setting (not a workaround) */ whitelist_mcr_reg(w, XEHP_COMMON_SLICE_CHICKEN3); - + whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); break; default: break; @@ -2087,7 +2100,7 @@ static void xelpg_whitelist_build(struct intel_engine_cs *engine) case RENDER_CLASS: /* Required by recommended tuning setting (not a workaround) */ whitelist_mcr_reg(w, XEHP_COMMON_SLICE_CHICKEN3); - + whitelist_reg(w, GEN7_COMMON_SLICE_CHICKEN1); break; default: break; -- 2.34.1
