> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Imre
> Deak
> Sent: Monday, July 22, 2024 10:25 PM
> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Subject: [PATCH 08/14] drm/i915/dp: Add helpers to set link training mode, BW
> parameters
>
> Add helpers to set the link mode and BW parameters. These are required by a
> follow-up patch setting the parameters for a disabled link.
>
> Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx>
LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@xxxxxxxxx>
> ---
> .../drm/i915/display/intel_dp_link_training.c | 34 +++++++++++++------
> .../drm/i915/display/intel_dp_link_training.h | 6 ++++
> 2 files changed, 29 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 57536ae200b77..214c8858b8a94 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -21,6 +21,8 @@
> * IN THE SOFTWARE.
> */
>
> +#include <drm/display/drm_dp_helper.h>
> +
> #include "i915_drv.h"
> #include "intel_display_types.h"
> #include "intel_dp.h"
> @@ -703,26 +705,28 @@ static bool
> intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
> return true;
> }
>
> -static void
> -intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,
> - const struct intel_crtc_state *crtc_state)
> +void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int
> +link_rate, bool is_vrr)
> {
> u8 link_config[2];
>
> - link_config[0] = crtc_state->vrr.flipline ?
> DP_MSA_TIMING_PAR_IGNORE_EN : 0;
> - link_config[1] = intel_dp_is_uhbr(crtc_state) ?
> + link_config[0] = is_vrr ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
> + link_config[1] = drm_dp_is_uhbr_rate(link_rate) ?
> DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
> drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL,
> link_config, 2); }
>
> -static void
> -intel_dp_update_link_bw_set(struct intel_dp *intel_dp,
> - const struct intel_crtc_state *crtc_state,
> - u8 link_bw, u8 rate_select)
> +static void intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,
> + const struct intel_crtc_state
> *crtc_state)
> {
> - u8 lane_count = crtc_state->lane_count;
> + intel_dp_link_training_set_mode(intel_dp,
> + crtc_state->port_clock, crtc_state-
> >vrr.flipline); }
>
> - if (crtc_state->enhanced_framing)
> +void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
> + int link_bw, int rate_select, int lane_count,
> + bool enhanced_framing)
> +{
> + if (enhanced_framing)
> lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
>
> if (link_bw) {
> @@ -746,6 +750,14 @@ intel_dp_update_link_bw_set(struct intel_dp
> *intel_dp,
> }
> }
>
> +static void intel_dp_update_link_bw_set(struct intel_dp *intel_dp,
> + const struct intel_crtc_state *crtc_state,
> + u8 link_bw, u8 rate_select)
> +{
> + intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, crtc_state-
> >lane_count,
> + crtc_state->enhanced_framing); }
> +
> /*
> * Prepare link training by configuring the link parameters. On DDI platforms
> * also enable the port here.
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> index 42e7fc6cb171a..2066b91467622 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> @@ -16,6 +16,12 @@ struct intel_dp;
> int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8
> dpcd[DP_RECEIVER_CAP_SIZE]); int intel_dp_init_lttpr_and_dprx_caps(struct
> intel_dp *intel_dp);
>
> +void intel_dp_link_training_set_mode(struct intel_dp *intel_dp,
> + int link_rate, bool is_vrr);
> +void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
> + int link_bw, int rate_select, int lane_count,
> + bool enhanced_framing);
> +
> void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state,
> enum drm_dp_phy dp_phy,
> --
> 2.44.2
