On Fri, Jun 07, 2024 at 03:12:40PM +0300, Jani Nikula wrote: > On Fri, 07 Jun 2024, Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> wrote: > > On Fri, Jun 07, 2024 at 01:51:28PM +0300, Jani Nikula wrote: > >> None of these are used. The parametrized register macros all depend on > >> the pipe/plane A offset macros alone. Remove the unused ones. > >> > >> Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx> > >> --- > >> drivers/gpu/drm/i915/i915_reg.h | 23 ----------------------- > >> 1 file changed, 23 deletions(-) > >> > >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > >> index 15ad35178f1a..2d834c32a3fa 100644 > >> --- a/drivers/gpu/drm/i915/i915_reg.h > >> +++ b/drivers/gpu/drm/i915/i915_reg.h > >> @@ -2214,29 +2214,6 @@ > >> #define SWF3(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4) > >> #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4) > >> > >> -/* Pipe B */ > >> -#define _PIPEBDSL (DISPLAY_MMIO_BASE(dev_priv) + 0x71000) > >> -#define _TRANSBCONF (DISPLAY_MMIO_BASE(dev_priv) + 0x71008) > >> -#define _PIPEBSTAT (DISPLAY_MMIO_BASE(dev_priv) + 0x71024) > >> -#define _PIPEBFRAMEHIGH 0x71040 > >> -#define _PIPEBFRAMEPIXEL 0x71044 > >> -#define _PIPEB_FRMCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71040) > >> -#define _PIPEB_FLIPCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71044) > >> - > > > > All the _ stuff should go for sure. > > > >> - > >> -/* Display B control */ > >> -#define _DSPBCNTR (DISPLAY_MMIO_BASE(dev_priv) + 0x71180) > >> -#define DISP_ALPHA_TRANS_ENABLE REG_BIT(15) > > > > Unlikely we'll ever use this, but if desired we could relocate > > this next to all the other DSPCNTR bits. With perhaps a note that > > it only applies to plane B. > > Huh. I can't actually find a platform where bit 15 would be "alpha trans > enable". It's either 180 degree rotation or decompression of compressed > surfaces. > > >> -#define DISP_SPRITE_ABOVE_OVERLAY REG_BIT(0) > > > > This too could be relocated, with a note that it only applies to plane > > B/C. Though as far as plane Z order goes I think there's at least one > > more bit for that we've not even defined, so this isn't super useful > > as is. > > And here it's either reserved or relocated rotation in bits 0-1. > > What am I missing? These only exist on gen2/3. i965 plane C still has the other Z order bit (2) that we haven't defined hus far. And by g4x it's all gone since plane C is also gone. -- Ville Syrjälä Intel
