From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
MTL has some new IOMMU thing that has a few new fault interrupts.
Enable those so we can know if things are going poorly.
Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/display/intel_display_irq.c | 10 ++++++++++
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 6eb14ffc3c1b..49bcba5e38cb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -835,6 +835,16 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
{
+ if (DISPLAY_VER(dev_priv) >= 14)
+ return MTL_PIPEDMC_ATS_FAULT |
+ MTL_PLANE_ATS_FAULT |
+ GEN12_PIPEDMC_FAULT |
+ GEN9_PIPE_CURSOR_FAULT |
+ GEN11_PIPE_PLANE5_FAULT |
+ GEN9_PIPE_PLANE4_FAULT |
+ GEN9_PIPE_PLANE3_FAULT |
+ GEN9_PIPE_PLANE2_FAULT |
+ GEN9_PIPE_PLANE1_FAULT;
if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))
return GEN12_PIPEDMC_FAULT |
GEN9_PIPE_CURSOR_FAULT |
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8cd5abc52a2d..33822816c27e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2627,12 +2627,14 @@
#define GEN8_PIPE_CDCLK_CRC_DONE REG_BIT(28)
#define GEN12_PIPEDMC_INTERRUPT REG_BIT(26) /* tgl+ */
#define GEN12_PIPEDMC_FAULT REG_BIT(25) /* tgl+ */
+#define MTL_PIPEDMC_ATS_FAULT REG_BIT(24) /* mtl+ */
#define XELPD_PIPE_SOFT_UNDERRUN REG_BIT(22) /* adl/dg2+ */
#define GEN11_PIPE_PLANE7_FAULT REG_BIT(22) /* icl/tgl */
#define XELPD_PIPE_HARD_UNDERRUN REG_BIT(21) /* adl/dg2+ */
#define GEN11_PIPE_PLANE6_FAULT REG_BIT(21) /* icl/tgl */
#define GEN11_PIPE_PLANE5_FAULT REG_BIT(20) /* icl+ */
#define GEN12_PIPE_VBLANK_UNMOD REG_BIT(19) /* tgl+ */
+#define MTL_PLANE_ATS_FAULT REG_BIT(18) /* mtl+ */
#define GEN11_PIPE_PLANE7_FLIP_DONE REG_BIT(18) /* icl/tgl */
#define GEN11_PIPE_PLANE6_FLIP_DONE REG_BIT(17) /* icl/tgl */
#define GEN11_PIPE_PLANE5_FLIP_DONE REG_BIT(16) /* icl+ */
--
2.44.1
