On Wed, Apr 03, 2024 at 04:52:39PM +0530, Balasubramani Vivekanandan wrote:
> Tables for eDP PHY PLL configuration for different link rates added for
> Xe2_HPD. Previous platforms were using C10 PHY for eDP port whereas
> Xe2_HPD has C20 PHY.
>
> Bpsec: 64568
I think 74165 would be more accurate?
Otherwise the tables below match the current spec, so
Reviewed-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
>
> CC: Clint Taylor <Clinton.A.Taylor@xxxxxxxxx>
> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 147 ++++++++++++++++++-
> 1 file changed, 146 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 6e4647859fc6..d948035f07ad 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -967,6 +967,148 @@ static const struct intel_c20pll_state * const mtl_c20_dp_tables[] = {
> NULL,
> };
>
> +/*
> + * eDP link rates with 38.4 MHz reference clock.
> + */
> +
> +static const struct intel_c20pll_state xe2hpd_c20_edp_r216 = {
> + .clock = 216000,
> + .tx = { 0xbe88,
> + 0x4800,
> + 0x0000,
> + },
> + .cmn = { 0x0500,
> + 0x0005,
> + 0x0000,
> + 0x0000,
> + },
> + .mpllb = { 0x50e1,
> + 0x2120,
> + 0x8e18,
> + 0xbfc1,
> + 0x9000,
> + 0x78f6,
> + 0x0000,
> + 0x0000,
> + 0x0000,
> + 0x0000,
> + 0x0000,
> + },
> +};
> +
> +static const struct intel_c20pll_state xe2hpd_c20_edp_r243 = {
> + .clock = 243000,
> + .tx = { 0xbe88,
> + 0x4800,
> + 0x0000,
> + },
> + .cmn = { 0x0500,
> + 0x0005,
> + 0x0000,
> + 0x0000,
> + },
> + .mpllb = { 0x50fd,
> + 0x2120,
> + 0x8f18,
> + 0xbfc1,
> + 0xa200,
> + 0x8814,
> + 0x2000,
> + 0x0001,
> + 0x1000,
> + 0x0000,
> + 0x0000,
> + },
> +};
> +
> +static const struct intel_c20pll_state xe2hpd_c20_edp_r324 = {
> + .clock = 324000,
> + .tx = { 0xbe88,
> + 0x4800,
> + 0x0000,
> + },
> + .cmn = { 0x0500,
> + 0x0005,
> + 0x0000,
> + 0x0000,
> + },
> + .mpllb = { 0x30a8,
> + 0x2110,
> + 0xcd9a,
> + 0xbfc1,
> + 0x6c00,
> + 0x5ab8,
> + 0x2000,
> + 0x0001,
> + 0x6000,
> + 0x0000,
> + 0x0000,
> + },
> +};
> +
> +static const struct intel_c20pll_state xe2hpd_c20_edp_r432 = {
> + .clock = 432000,
> + .tx = { 0xbe88,
> + 0x4800,
> + 0x0000,
> + },
> + .cmn = { 0x0500,
> + 0x0005,
> + 0x0000,
> + 0x0000,
> + },
> + .mpllb = { 0x30e1,
> + 0x2110,
> + 0x8e18,
> + 0xbfc1,
> + 0x9000,
> + 0x78f6,
> + 0x0000,
> + 0x0000,
> + 0x0000,
> + 0x0000,
> + 0x0000,
> + },
> +};
> +
> +static const struct intel_c20pll_state xe2hpd_c20_edp_r675 = {
> + .clock = 675000,
> + .tx = { 0xbe88,
> + 0x4800,
> + 0x0000,
> + },
> + .cmn = { 0x0500,
> + 0x0005,
> + 0x0000,
> + 0x0000,
> + },
> + .mpllb = { 0x10af,
> + 0x2108,
> + 0xce1a,
> + 0xbfc1,
> + 0x7080,
> + 0x5e80,
> + 0x2000,
> + 0x0001,
> + 0x6400,
> + 0x0000,
> + 0x0000,
> + },
> +};
> +
> +static const struct intel_c20pll_state * const xe2hpd_c20_edp_tables[] = {
> + &mtl_c20_dp_rbr,
> + &xe2hpd_c20_edp_r216,
> + &xe2hpd_c20_edp_r243,
> + &mtl_c20_dp_hbr1,
> + &xe2hpd_c20_edp_r324,
> + &xe2hpd_c20_edp_r432,
> + &mtl_c20_dp_hbr2,
> + &xe2hpd_c20_edp_r675,
> + &mtl_c20_dp_hbr3,
> + NULL,
> +};
> +
> /*
> * HDMI link rates with 38.4 MHz reference clock.
> */
> @@ -2084,7 +2226,10 @@ intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state,
> struct intel_encoder *encoder)
> {
> if (intel_crtc_has_dp_encoder(crtc_state))
> - return mtl_c20_dp_tables;
> + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> + return xe2hpd_c20_edp_tables;
> + else
> + return mtl_c20_dp_tables;
> else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> return mtl_c20_hdmi_tables;
>
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
