On Tue, 2024-02-06 at 15:25 +0000, Murthy, Arun R wrote: > > > -----Original Message----- > > From: Hogander, Jouni <jouni.hogander@xxxxxxxxx> > > Sent: Tuesday, January 30, 2024 4:41 PM > > To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx > > Cc: Murthy, Arun R <arun.r.murthy@xxxxxxxxx>; Hogander, Jouni > > <jouni.hogander@xxxxxxxxx>; Nikula, Jani <jani.nikula@xxxxxxxxx> > > Subject: [PATCH v3 1/4] drm/i915/alpm: Add ALPM register > > definitions > > > > Add ALPM register definitions for Lunar Lake. > > > > v3: > > - Fix ALPM_CTL2_A address > > - Remove duplicate defines > > v2: > > - Use REG_BIT instead of BIT > > - Add commit message > > > > Cc: Jani Nikula <jani.nikula@xxxxxxxxx> > > > > Signed-off-by: Jouni Högander <jouni.hogander@xxxxxxxxx> > > --- > Reviewed-by: Arun R Murthy <arun.r.murthy@xxxxxxxxx> Thank you Arun for your review. These are now pushed to drm-intel-next. BR, Jouni Högander > > Thanks and Regards, > Arun R Murthy > -------------------- > > drivers/gpu/drm/i915/display/intel_psr_regs.h | 57 > > +++++++++++++++++++ > > 1 file changed, 57 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h > > b/drivers/gpu/drm/i915/display/intel_psr_regs.h > > index bc252f38239e..8427a736f639 100644 > > --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h > > +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h > > @@ -296,4 +296,61 @@ > > > > _SEL_FETCH_PLANE_OFFSET_1_A - \ > > > > _SEL_FETCH_PLANE_BASE_1_A) > > > > +#define _ALPM_CTL_A 0x60950 > > +#define ALPM_CTL(tran) _MMIO_TRANS2(tran, _ALPM_CTL_A) > > +#define ALPM_CTL_ALPM_ENABLE REG_BIT(31) > > +#define ALPM_CTL_ALPM_AUX_LESS_ENABLE REG_BIT(30) > > +#define ALPM_CTL_LOBF_ENABLE REG_BIT(29) > > +#define ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE REG_BIT(28) > > +#define ALPM_CTL_KEEP_FEC_ENABLE_FOR_AUX_WAKE_SLEEP REG_BIT(27) > > +#define ALPM_CTL_RESTORE_OCCURED REG_BIT(26) > > +#define ALPM_CTL_RESTORE_TO_SLEEP REG_BIT(25) > > +#define > > ALPM_CTL_RESTORE_TO_DEEP_SLEEP REG_BIT(24) > > +#define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK > > REG_GENMASK(23, 21) > > +#define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS > > REG_FIELD_PREP(ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK, 0) > > +#define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_128_SYMBOLS > > REG_FIELD_PREP(ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK, 1) > > +#define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_256_SYMBOLS > > REG_FIELD_PREP(ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK, 2) > > +#define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_512_SYMBOLS > > REG_FIELD_PREP(ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK, 3) > > +#define ALPM_CTL_AUX_WAKE_SLEEP_HOLD_ENABLE REG_BIT(20) > > +#define ALPM_CTL_ALPM_ENTRY_CHECK_MASK > > REG_GENMASK(19, 16) > > +#define ALPM_CTL_ALPM_ENTRY_CHECK(val) > > REG_FIELD_PREP(ALPM_CTL_ALPM_ENTRY_CHECK_MASK, val) > > +#define ALPM_CTL_EXTENDED_FAST_WAKE_TIME_MASK > > REG_GENMASK(13, 8) > > +#define ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES 5 > > +#define ALPM_CTL_EXTENDED_FAST_WAKE_TIME(lines) > > REG_FIELD_PREP(ALPM_CTL_EXTENDED_FAST_WAKE_TIME_MASK, > > (lines) - ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES) > > +#define ALPM_CTL_AUX_LESS_WAKE_TIME_MASK > > REG_GENMASK(5, 0) > > +#define ALPM_CTL_AUX_LESS_WAKE_TIME(val) > > REG_FIELD_PREP(ALPM_CTL_AUX_LESS_WAKE_TIME_MASK, val) > > + > > +#define _ALPM_CTL2_A 0x60954 > > +#define ALPM_CTL2(tran) _MMIO_TRANS2(tran, _ALPM_CTL2_A) > > +#define ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK > > REG_GENMASK(28, 24) > > +#define ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY(val) > > REG_FIELD_PREP(ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK, > > val) > > +#define ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION_MASK > > REG_GENMASK(19, 16) > > +#define ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION(val) > > REG_FIELD_PREP(ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION_MA > > SK, val) > > +#define ALPM_CTL2_NUMBER_OF_LTTPR_MASK > > REG_GENMASK(15, 12) > > +#define ALPM_CTL2_NUMBER_OF_LTTPR(val) > > REG_FIELD_PREP(ALPM_CTL2_NUMBER_OF_LTTPR_MASK, val) > > +#define ALPM_CTL2_LTTPR_AUX_LESS_SLEEP_HOLD_TIME_MASK > > REG_GENMASK(10, 8) > > +#define ALPM_CTL2_LTTPR_AUX_LESS_SLEEP_HOLD_TIME(val) > > REG_FIELD_PREP(ALPM_CTL2_LTTPR_AUX_LESS_SLEEP_HOLD_TIME_M > > ASK, val) > > +#define ALPM_CTL2_FEC_DECODE_EN_POSITION_AFTER_WAKE_SR > > REG_BIT(4) > > +#define > > ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES_MASK > > REG_GENMASK(2, 0) > > +#define ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES(val) > > REG_FIELD_PREP(ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SE > > QUENCES_MASK, val) > > + > > +#define _PORT_ALPM_CTL_A 0x16fa2c > > +#define PORT_ALPM_CTL(tran) _MMIO_TRANS2(tran, > > _PORT_ALPM_CTL_A) > > +#define PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE REG_BIT(31) > > +#define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK > > REG_GENMASK(23, 20) > > +#define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(val) > > REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK, > > val) > > +#define PORT_ALPM_CTL_MAX_PHY_SWING_HOLD_MASK > > REG_GENMASK(19, 16) > > +#define PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(val) > > REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_HOLD_MASK, > > val) > > +#define PORT_ALPM_CTL_SILENCE_PERIOD_MASK REG_GENMASK(7, 0) > > +#define PORT_ALPM_CTL_SILENCE_PERIOD(val) > > REG_FIELD_PREP(PORT_ALPM_CTL_SILENCE_PERIOD_MASK, val) > > + > > +#define _PORT_ALPM_LFPS_CTL_A > > 0x16fa30 > > +#define PORT_ALPM_LFPS_CTL(tran) > > _MMIO_TRANS2(tran, _PORT_ALPM_LFPS_CTL_A) > > +#define PORT_ALPM_LFPS_CTL_LFPS_START_POLARITY > > REG_BIT(31) > > +#define PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK > > REG_GENMASK(27, 24) > > +#define ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES 5 > > +#define ALPM_CTL_EXTENDED_FAST_WAKE_TIME(lines) > > REG_FIELD_PREP(ALPM_CTL_EXTENDED_FAST_WAKE_TIME_MASK, > > (lines) - ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES) > > +#define ALPM_CTL_AUX_LESS_WAKE_TIME_MASK > > REG_GENMASK(5, 0) > > +#define ALPM_CTL_AUX_LESS_WAKE_TIME(val) > > REG_FIELD_PREP(ALPM_CTL_AUX_LESS_WAKE_TIME_MASK, val) > > + > > #endif /* __INTEL_PSR_REGS_H__ */ > > -- > > 2.34.1 >
