Apply the correct BW allocation overhead and channel coding efficiency
on UHBR link rates, similarly to DP1.4 link rates.
Reviewed-by: Arun R Murthy <arun.r.murthy@xxxxxxxxx>
Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx>
---
drivers/gpu/drm/i915/display/intel_display.c | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1e045e4fbe582..9755e0a5042c4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2398,16 +2398,6 @@ add_bw_alloc_overhead(int link_clock, int bw_overhead,
int ch_coding_efficiency =
drm_dp_bw_channel_coding_efficiency(is_uhbr);
- /*
- * TODO: adjust for actual UHBR channel coding efficiency and BW
- * overhead.
- */
- if (is_uhbr) {
- *data_m = pixel_data_rate;
- *data_n = link_data_rate * 8 / 10;
- return;
- }
-
*data_m = DIV_ROUND_UP_ULL(mul_u32_u32(pixel_data_rate, bw_overhead),
1000000);
*data_n = DIV_ROUND_DOWN_ULL(mul_u32_u32(link_data_rate, ch_coding_efficiency),
--
2.39.2
