From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Use the recommended PLL dividers from
VLV2_DPLL_mphy_hsdpll_frequency_table_ww6_rev1p1.xlsm. The previous
values were really bogus. The 2.7 values look good however.
Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 5e1de35..a5e4e61 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -59,7 +59,7 @@ static const struct dp_link_dpll pch_dpll[] = {
static const struct dp_link_dpll vlv_dpll[] = {
{ DP_LINK_BW_1_62,
- { .p1 = 3, .p2 = 2, .n = 5, .m1 = 5, .m2 = 3 } },
+ { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
{ DP_LINK_BW_2_7,
{ .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
};
--
1.8.1.5
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