ville.syrjala@xxxxxxxxxxxxxxx writes: > I only wanted to do some small cleanups to vlv_find_best_dpll(), > but it seems I went slightly mad again. > > After realizing that I have to cook up quite a few more patches, > I decided to also split up the functional changes from my earlier > vlv_find_best_dpll() rewrite patch. And this series is the result. > > And the usual warning applies: Totally untested > > Ville Syrjälä (14): > drm/i915: Eliminate one indent leel from vlv_find_best_dpll > drm/i915: Use DIV_ROUND_CLOSEST() > drm/i915: Make vlv_find_best_dpll() ppm calculation safe > drm/i915: Don't underflow bestppm > drm/i915: Rewrite vlv_find_best_dpll() > drm/i915: De-magic the VLV p2 divider step size > drm/i915: Make sure we respect n.max on VLV > drm/i915: Clarify VLV PLL p1 limits > drm/i915: Allow p1 divider 2 on VLV > drm/i915: Respect p2 divider minimum limit on VLV > drm/i915: Remove the unused p and m limits for VLV > drm/i915: Remove unused dot_limit from VLV PLL limits > drm/i915: intel_limits_vlv_dac and intel_limits_vlv_hdmi are the same > drm/i915: Don't lie about findind suitable PLL settings on VLV > > drivers/gpu/drm/i915/intel_display.c | 123 +++++++++++++++++++++++++++++++++++---------------------------------------------------- > 1 file changed, 49 insertions(+), 74 deletions(-) > I have read these through and tested the algorithm against the values in the freq table excel sheet. The pre-patchset algorithm sometimes skipped large but valid p1 values due to underflow of bestppm - 10. Patch 04/15 fixes this issue. After Ville's patches the find_best_dpll() seems to match exactly against what the sheet gives. Atleast on selected set of rates. And the whole thing is much more readable now, so: Patches: 3-4, 5 v3, 6-14 and 15/14 Reviewed-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxx> _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
