From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Rebase of the ICL+ DSI modeset sequence stuff.
Ville Syrjälä (13):
drm/i915/dsi: Do panel power on + reset deassert earlier on icl+
drm/i915/dsi: Do display on sequence later on icl+
drm/i915/dsi: Print the VBT MIPI sequence delay duration
drm/i915/dsi: Split icl+ D-PHY vs. DSI timing steps
drm/i915/dsi: Gate DSI clocks earlier
drm/i915/dsi: Respect power cycle delay on icl+
drm/i915/dsi: Implement encoder->shutdown() for icl+
drm/i915/dsi: Move most things from .disable() into .post_disable() on
icl+
drm/i915/dsi: Do DSC/scaler disable earlier on icl+
drm/i915/dsi: Respect power_off_delay on icl+
drm/i915/dsi: Move panel reset+power off to be the last thing
drm/i915/dsi: Grab the crtc from the customary place
drm/i915/dsi: Remove weird has_pch_encoder asserts
drivers/gpu/drm/i915/display/icl_dsi.c | 127 +++++++++++--------
drivers/gpu/drm/i915/display/intel_dsi.c | 20 +++
drivers/gpu/drm/i915/display/intel_dsi.h | 2 +
drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 2 +-
drivers/gpu/drm/i915/display/vlv_dsi.c | 23 ----
5 files changed, 100 insertions(+), 74 deletions(-)
--
2.39.3
