On 02.09.2013 16:18, Daniel Vetter wrote:
Checked with the above modifications. Unfortunately, the result is
negative. With the above modifications and my changes commented out,
the screen flickers in normal state (without panning) but in a
different way: With the above enabled, you get a rather irregular
almost pseudo-random flicker, and not the 60/30Hz flicker I see when
panning horizontally. If I add horizontal panning, then I also get
this irregular flicker, except when scrolling to the "forbidden
positions" at which I get the regular hi-frequency flicker again.
Hm, I've probably botched the watermarks again. Can you please retest with
the below diff?
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index dfdc7ad..b667ff0 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1064,6 +1064,8 @@ static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
+ wm_size = 0;
+
/* Don't promote wm_size to unsigned... */
if (wm_size> (long)wm->max_wm)
wm_size = wm->max_wm;
Not much difference, probably in the type of flicker. Very unstable,
pseudo-random flicker at offset = 0, which gets a bit better for
somewhat larger positions, but still the high-frequency flicker at
forbidden positions. The flicker type definitely depends on the scroll
position, but the high-freq flicker at (x & 16) != 0 does not go away
neither did it change in any way. )-: Only the flicker frequency at
positions (x & 16) == 0 did change, and then depends on (x & 15).
The kms api doesn't really allow for such information to be passed around.
And since current userspace expects this to Just Work we need to be rather
careful with such hacks. Since the docs don't mention any such requirement
I think we should try a bit and figure out whether changing the watermarks
fixes this.
Is there anything I could do to confirm that the high-freq flicker is
really due to watermarks? Since the above modifications do not really
seem to work. It might also be that the amount of prefetch the FIFO
requires depends on the memory alignment as in "prefetch must occur
starting from first 256-bit aligned position" or something?
Greetings,
Thomas
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