On Tue, Aug 27, 2013 at 11:39:52AM +0200, Daniel Vetter wrote: > Patch 17: Should be tested by someone else with a gt3. Who has one? More missing mails, I haven't got the patch to comment on, so bare with me. The title and changelog is misleading, this is not about enabling Lower Slice at all. Something like: "drm/i915: Report enabled slices on Haswell GT3 Batchbuffers constructed by userspace can conditionalise their URB allocations through the use of the MI_SET_PREDICATE command. This command can read the MI_PREDICATE_RESULT_2 register to see how many slices are enabled on GT3, and by virtue of the result, scale their memory allocations to fit enabled memory. Of course, this only works if the kernel sets the appropriate bit in the register first." This doesn't attempt to explain the complexity of why we have the same informatiom in multiple registers and why the hw designers thought it wise for sw to keep them all in sync... -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
