On Thu, Feb 02, 2023 at 07:05:27PM +0000, Manna, Animesh wrote:
>
>
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Ville
> > Syrjala
> > Sent: Wednesday, January 18, 2023 10:01 PM
> > To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> > Subject: [PATCH 11/13] drm/i915/dsb: Write each legacy LUT entry
> > twice with DSB
> >
> > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> >
> > The DSB has problems loading the legacy LUT. Looks like simply writing each
> > LUT entry twice back-to-back is sufficient workaround for this.
> >
> > Curiously it doesn't even matter what data we provide for the first write, the
> > second write always seems to work 100%. So this doesn't seem to be some
> > kind of simple race where the data gets latched before it's actually available
> > on some bus (which was my first hunch).
> >
> > TODO: need to figure out what is the actual hw issue here
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/display/intel_color.c | 11 ++++++++++-
> > 1 file changed, 10 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> > b/drivers/gpu/drm/i915/display/intel_color.c
> > index 4c3344ee473e..8de2dc4b7904 100644
> > --- a/drivers/gpu/drm/i915/display/intel_color.c
> > +++ b/drivers/gpu/drm/i915/display/intel_color.c
> > @@ -860,9 +860,18 @@ static void ilk_load_lut_8(const struct
> > intel_crtc_state *crtc_state,
> >
> > lut = blob->data;
> >
> > - for (i = 0; i < 256; i++)
> > + for (i = 0; i < 256; i++) {
> > + /*
> > + * DSB fails to correctly load the legacy
> > + * LUT unless we write each entry twice.
> > + * It doesn't actually matter what data we
> > + * provide for the first write.
> > + */
>
> Is it confirmed by hardware team?
Haven't filed the hsd yet on account of being busy debugging
other DSB issues. But I should do that soon.
> Is there any difference with indexed register write and single register write.
It doesn't matter what kind of write you use. I also tried all
various other tricks (eg. the non-posted write stuff, and just
slowing things down with other registers writes, etc.).
--
Ville Syrjälä
Intel
