> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, January 18, 2023 10:01 PM
> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Subject: [PATCH 11/13] drm/i915/dsb: Write each legacy LUT entry
> twice with DSB
>
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> The DSB has problems loading the legacy LUT. Looks like simply writing each
> LUT entry twice back-to-back is sufficient workaround for this.
>
> Curiously it doesn't even matter what data we provide for the first write, the
> second write always seems to work 100%. So this doesn't seem to be some
> kind of simple race where the data gets latched before it's actually available
> on some bus (which was my first hunch).
>
> TODO: need to figure out what is the actual hw issue here
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 11 ++++++++++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 4c3344ee473e..8de2dc4b7904 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -860,9 +860,18 @@ static void ilk_load_lut_8(const struct
> intel_crtc_state *crtc_state,
>
> lut = blob->data;
>
> - for (i = 0; i < 256; i++)
> + for (i = 0; i < 256; i++) {
> + /*
> + * DSB fails to correctly load the legacy
> + * LUT unless we write each entry twice.
> + * It doesn't actually matter what data we
> + * provide for the first write.
> + */
Is it confirmed by hardware team? Is there any difference with indexed register write and single register write.
Regards,
Animesh
> + if (crtc_state->dsb)
> + ilk_lut_write(crtc_state, LGC_PALETTE(pipe, i), 0);
> ilk_lut_write(crtc_state, LGC_PALETTE(pipe, i),
> i9xx_lut_8(&lut[i]));
> + }
> }
>
> static void ilk_load_lut_10(const struct intel_crtc_state *crtc_state,
> --
> 2.38.2
