On Wed, Dec 07, 2022 at 11:34:43AM +0200, Jani Nikula wrote: > None of the remaining backlight registers that use DISPLAY_MMIO_BASE() > are used on VLV/CHV, which are the only platforms that have non-zero > base. Just drop the DISPLAY_MMIO_BASE() use, reducing the implicit > dev_priv references. Will we be able to entirely kill the display_mmio_base and the implict references? I have the feeling we are one step closer... anything blocking in your view? Reviewed-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> > > Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx> > --- > drivers/gpu/drm/i915/display/intel_backlight_regs.h | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_backlight_regs.h b/drivers/gpu/drm/i915/display/intel_backlight_regs.h > index 02bd1f8201bf..d0cdfd631d75 100644 > --- a/drivers/gpu/drm/i915/display/intel_backlight_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_backlight_regs.h > @@ -21,7 +21,7 @@ > #define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, _VLV_BLC_HIST_CTL_B) > > /* Backlight control */ > -#define BLC_PWM_CTL2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61250) /* 965+ only */ > +#define BLC_PWM_CTL2 _MMIO(0x61250) /* 965+ only */ > #define BLM_PWM_ENABLE (1 << 31) > #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */ > #define BLM_PIPE_SELECT (1 << 29) > @@ -44,7 +44,7 @@ > #define BLM_PHASE_IN_COUNT_MASK (0xff << 8) > #define BLM_PHASE_IN_INCR_SHIFT (0) > #define BLM_PHASE_IN_INCR_MASK (0xff << 0) > -#define BLC_PWM_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61254) > +#define BLC_PWM_CTL _MMIO(0x61254) > /* > * This is the most significant 15 bits of the number of backlight cycles in a > * complete cycle of the modulated backlight control. > @@ -66,7 +66,7 @@ > #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe) > #define BLM_POLARITY_PNV (1 << 0) /* pnv only */ > > -#define BLC_HIST_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260) > +#define BLC_HIST_CTL _MMIO(0x61260) > #define BLM_HISTOGRAM_ENABLE (1 << 31) > > /* New registers for PCH-split platforms. Safe where new bits show up, the > -- > 2.34.1 >
