Re: [PATCH v3] drm/i915/mtl: Enable Idle Messaging for GSC CS

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On 19-11-2022 00:07, Vivi, Rodrigo wrote:
On Sat, 2022-11-19 at 00:03 +0530, Badal Nilawar wrote:
From: Vinay Belgaumkar <vinay.belgaumkar@xxxxxxxxx>

By defaut idle messaging is disabled for GSC CS so to unblock RC6
entry on media tile idle messaging need to be enabled.

v2:
  - Fix review comments (Vinay)
  - Set GSC idle hysteresis as per spec (Badal)
v3:
  - Fix review comments (Rodrigo)

Bspec: 71496

Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@xxxxxxxxx>
Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@xxxxxxxxx>
Signed-off-by: Badal Nilawar <badal.nilawar@xxxxxxxxx>
Reviewed-by: Vinay Belgaumkar <vinay.belgaumkar@xxxxxxxxx>

He is the author of the patch, no?!
or you can remove this or change the author to be you and keep his
reviewed-by...

or I can just remove his rv-b while merging.. just let me know..
As he is original author I will prefer not to change it. You can remove his rv-b while merging.

Regards,
Badal

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
---
  drivers/gpu/drm/i915/gt/intel_engine_pm.c | 18 ++++++++++++++++++
  drivers/gpu/drm/i915/gt/intel_gt_regs.h   |  4 ++++
  2 files changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index b0a4a2dbe3ee..e971b153fda9 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -15,6 +15,22 @@
  #include "intel_rc6.h"
  #include "intel_ring.h"
  #include "shmem_utils.h"
+#include "intel_gt_regs.h"
+
+static void intel_gsc_idle_msg_enable(struct intel_engine_cs
*engine)
+{
+       struct drm_i915_private *i915 = engine->i915;
+
+       if (IS_METEORLAKE(i915) && engine->id == GSC0) {
+               intel_uncore_write(engine->gt->uncore,
+                                  RC_PSMI_CTRL_GSCCS,
+
_MASKED_BIT_DISABLE(IDLE_MSG_DISABLE));
+               /* hysteresis 0xA=5us as recommended in spec*/
+               intel_uncore_write(engine->gt->uncore,
+                                  PWRCTX_MAXCNT_GSCCS,
+                                  0xA);
+       }
+}
 static void dbg_poison_ce(struct intel_context *ce)
  {
@@ -275,6 +291,8 @@ void intel_engine_init__pm(struct intel_engine_cs
*engine)
        intel_wakeref_init(&engine->wakeref, rpm, &wf_ops);
         intel_engine_init_heartbeat(engine);
+
+       intel_gsc_idle_msg_enable(engine);
  }
 /**
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index c3cd92691795..80a979e6f6be 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -917,6 +917,10 @@
  #define  MSG_IDLE_FW_MASK      REG_GENMASK(13, 9)
  #define  MSG_IDLE_FW_SHIFT     9
+#define        RC_PSMI_CTRL_GSCCS      _MMIO(0x11a050)
+#define          IDLE_MSG_DISABLE      REG_BIT(0)
+#define        PWRCTX_MAXCNT_GSCCS     _MMIO(0x11a054)
+
  #define FORCEWAKE_MEDIA_GEN9                   _MMIO(0xa270)
  #define FORCEWAKE_RENDER_GEN9                  _MMIO(0xa278)




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