2013/7/24 Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>: > On Tue, Jul 23, 2013 at 07:33:43PM -0300, Paulo Zanoni wrote: >> From: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx> >> >> The problem here is that we have the PIPESTAT registers between IER >> and IIR, so when we use intel_irq_reg_reset we flip the order used to >> reset IIR and PIPESTAT. That should be safe since after we clear >> IMR/IER we won't get any other IIR/PIPESTAT interrupts. Still, the >> change is on its own patch, so it should be easy to bisect and revert >> if needed. > > This is wrong. PIPESTAT needs to be cleared before IIR. Yeah, you're right. I see that if we want to make all the code touching pipestat consistent we could probably dedicate a full patch series to it. The fact that PIPESTAT needs to be disabled after IER/IMR but before IIR also kinda breaks my macros, I'll have to rethink them now. Thanks for the review! > -Chris > > -- > Chris Wilson, Intel Open Source Technology Centre -- Paulo Zanoni _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
