On Tue, Jul 23, 2013 at 07:33:43PM -0300, Paulo Zanoni wrote: > From: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx> > > The problem here is that we have the PIPESTAT registers between IER > and IIR, so when we use intel_irq_reg_reset we flip the order used to > reset IIR and PIPESTAT. That should be safe since after we clear > IMR/IER we won't get any other IIR/PIPESTAT interrupts. Still, the > change is on its own patch, so it should be easy to bisect and revert > if needed. This is wrong. PIPESTAT needs to be cleared before IIR. -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
