On Wed, Jul 24, 2013 at 10:00:49AM -0300, Paulo Zanoni wrote: > 2013/7/24 Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>: > > On Tue, Jul 23, 2013 at 07:33:44PM -0300, Paulo Zanoni wrote: > >> From: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx> > >> > >> As written on our docs, the IIR registers are capable of storing 2 > >> interrupts, so if we write once to them there's no guarantee they will > >> become zero. So on this patch we write to the register, read to check > >> if it's zero, and then write again in case it's needed. > >> > >> Also replace I915_WRITE(iir, I915_READ(iir)) with I915_WRITE(iir, > >> 0xffffffff), and then move the POSTING_READs on IER because we removed > >> the extra IIR read. > > > > Just write(read(iir)) twice and add a comment why. > > Just to clarify: why not write(iir, 0xffffffff) twice to save the 2 reads? Force of habit... You occassionally come across some register that mixes a toggle with a status pin - so you only set what is asserted so that you clear the status pins without enabling anything else. I don't think that applies to these but you are covering over a decade of hw engineering with many lost secrets... -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
