From: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx>
As written on our docs, the IIR registers are capable of storing 2
interrupts, so if we write once to them there's no guarantee they will
become zero. So on this patch we write to the register, read to check
if it's zero, and then write again in case it's needed.
Also replace I915_WRITE(iir, I915_READ(iir)) with I915_WRITE(iir,
0xffffffff), and then move the POSTING_READs on IER because we removed
the extra IIR read.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx>
---
drivers/gpu/drm/i915/i915_irq.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b1b6552..29eac7a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -82,10 +82,14 @@ static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
#define INTEL_IRQ_REG_RESET(type, do_iir) do { \
I915_WRITE(type##MR, 0xffffffff); \
I915_WRITE(type##ER, 0); \
- if (do_iir) \
- I915_WRITE(type##IR, I915_READ(type##IR)); \
- else \
- POSTING_READ(type##ER); \
+ POSTING_READ(type##ER); \
+ if (do_iir) { \
+ I915_WRITE(type##IR, 0xffffffff); \
+ if (I915_READ(type##IR)) { \
+ I915_WRITE(type##IR, 0xffffffff); \
+ POSTING_READ(type##IR); \
+ } \
+ } \
} while (0)
/* For display hotplug interrupt */
--
1.8.1.2
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