I don't have a strong opinion on iris x crw and you know that I like to split different things in different functions, however in this case I think either iris or crw are still hsw so if it is possible to get dev_priv->ellc_size inside hsw_pte_encode somehow I in favor of not creating another function for iris... otherwise, fell free to use: Reviewed-by: Rodrigo Vivi <rodrigo.vivi at gmail.com> On Thu, Jul 4, 2013 at 3:40 PM, Ben Widawsky <ben at bwidawsk.net> wrote: > On Thu, Jul 04, 2013 at 08:17:09PM +0200, Daniel Vetter wrote: >> On Thu, Jul 04, 2013 at 11:02:06AM -0700, Ben Widawsky wrote: >> > DRI clients really should be using MOCS to get fine grained streaming >> > cache controls. With that note, I *hope* that this patch doesn't improve >> > performance overwhelmingly, because if it does - it means there is a >> > problem elsewhere. >> > >> > In any case, the kernel, and old userspace should get some benefit from >> > this, so let's do it. eLLC is always a good default, and really not >> > using it is the special case for MOCS. >> > >> > References: http://www.intel.com/newsroom/kits/restricted/ha$well!/pdfs/4th_Gen_Intel_Core_PressBriefing_5-29.pdf (page 57) >> > >> > Signed-off-by: Ben Widawsky <ben at bwidawsk.net> >> >> Iris is the marketing name and likely to stick around for a bit (like HD >> Graphics), I'd vote to use the codename for this thing here, i.e. crw. >> -Daniel >> > I think we've agreed on IRC to leave this as is? > -- > Ben Widawsky, Intel Open Source Technology Center > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Rodrigo Vivi Blog: http://blog.vivi.eng.br
